9-1
9-2
9-3
Possible causes for the CPU memory reset request ..................................9-13
9-4
Procedure for resetting the CPU memory...................................................9-13
9-5
9-6
Software requirements ................................................................................9-22
9-7
9-8
Event recognition by CPUs 31x-2 DP/31xC-2 DP as the DP master .........9-25
9-9
Event recognition for CPUs 31x-2 DP/31xC-2 DP as the DP slave............9-28
9-10
Configuration example for the address areas in intermediate memory .....9-29
10-1
10-2
11-1
The differences between forcing and modifying variables .........................11-3
11-2
Status and error displays ...........................................................................11-7
11-3
11-4
Evaluation of the SF LED (hardware error)................................................11-9
11-5
11-6
11-7
The BUSF LED flashes ............................................................................11-11
11-8
11-9
Evaluation in the DP master of RUN to STOP transitions by the
DP slave ...................................................................................................11-14
11-10
Reading the diagnostic information using STEP 5 and STEP 7
in the masters system ..............................................................................11-16
11-11
11-12
Evaluation of RUN to STOP transitions in the DP master/DP slave........11-20
11-13
11-14
Structure of station status 2 (byte 1) ........................................................11-23
11-15
11-16
Structure of the master PROFIBUS address (byte 3) ..............................11-24
11-17
Structure of the vendor ID (byte 4, 5).......................................................11-24
12-1
12-2
Mains voltage .............................................................................................12-2
12-3
Protection against external electrical interference .....................................12-2
12-4
Protection against external electrical interference .....................................12-2
12-5
Coupling mechanisms ................................................................................12-4
12-6
Key to example 1......................................................................................12-10
12-7
12-8
High-voltage protection of cables with surge voltage protection
components ..............................................................................................12-21
12-9
Surge voltage protection components for lightning protection
zones 1 <-> 2 ...........................................................................................12-23
12-10
Surge voltage protection components for lightning protection
zones 2 <-> 3 ...........................................................................................12-24
12-11
S7-300 Automation System, Hardware and Installation: CPU 31xC and CPU 31x
A5E00105492-03
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