Sdi7 Dual Channel Sd/Hd/3G Sdi Video Generatortheory Of Operation; Overview; Fpga And Associated Circuits - Tektronix TG700 Service Manual

SDI7 Dual Channel SD/HD/3G SDI Video Generator
Theory of Operation

Overview

FPGA and Associated Circuits

Signal Generation
TG700 TV Signal Generator Platform Service Manual
This section describes the basic operation of the major circuit blocks in the SDI7
module. The discussions relate to the Block Diagram. (See Figure 13-1.)
There is some circuitry on the SDI7 Main circuit board which is not used. Unused
circuitry is not represented in the block diagram, nor is it discussed in this theory
of operation.
The SDI7 module has four circuit boards: the main module board, which mounts
horizontally and contains the bulk of the circuitry, and three small output boards.
These output boards plug into the main board vertically and provide the rear BNC
connections and the circuits required to buffer the high-speed output signals.
The heart of the SDI7 generator is an FPGA, with other circuits that provide
support and ancillary functions. For signal generation, the FPGA creates the
output signal such as color bars or a ramp. For some signals, the information to
create the signals is completely contained within the FPGA. For other signals,
data from the memories is used as well. Serialization and scrambling is also
done in the FPGA.
A Programmable Logic Device (PLD) configures the FPGA by loading a file from
the Flash at power up. This configures the FPGA for normal operation; there is
a separate file for calibration.
The CPU interface connects to both the PLD and FPGA. During SW upgrade, the
Flash files are loaded from the mainframe via the PLD. The FPGA uses the CPU
connection to access the control registers.
The FPGA contains horizontal and vertical counters which create the raster
structure for the selected signal. For most test signals, these counters drive the
FPGA elements that create the actual video signals such as color bars or flat field,
along with the EAV and SAV info and CRCs if appropriate. The video signals
are then scrambled, serialized, and sent at 270 Mb/s, 1.5 Gb/s or 3 Gb/s from
the FPGA to the output boards.
When generating frame picture signals, similar horizontal and vertical counters
access the DDR memory for the given channel. In this mode, the data from the
user's picture file is used to create the test signal. This data stream is combined
with the standard test signal stream to add the other required elements and the
result is then serialized.
13–1