SOLTEK 82440FX User Manual page 28

DRAM RAS#
Precharge Time
RAS# to CAS#
Delay
DRAM Read Burst
(B/E/F)
DRAM Write Burst
(B/E/F)
ISA Bus Clock
DRAM Refresh
Queue
DRAM RAS Only
Refresh
ECC Checking/
Generation
Fast Dram Refresh Use the default setting.
Read-Around-
Write
PCI Burst Write
Combine
PCI-TO-DRAM
Pipeline
28
Use the default setting. This option
allows you to determine the number
of the CPU clocks allocated for the
RAS to accumulate/charge it before
the DRAM is refreshed.
Use the default setting. This setup
option allows you to determine the
delay time in completing the
transition from RAS to CAS.
Use the default setting. Burst
read/write requests are generated
by the CPU in four separate parts.
The 1st part provides the location
within the DRAM where the read or
write is to take place while the
remaining three parts provide the
actual data. The lower the timing
number is, the faster the system
memory will be addressed.
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.