The external interrupts take place on a transition of the input, which is programmable for
rising, falling or both edges. The pulse catchers are programmable separately to detect a
rising, falling, or either edge in the input. Each of the interrupt pins has its own catcher
device to catch the edge transition and request the interrupt.
When the interrupt takes place, both pulse catchers associated with that interrupt are auto-
matically reset. If both edges are detected before the corresponding interrupt takes place,
because the triggering edges occur nearly simultaneously or because the interrupts are
inhibited by the processor priority, then there will be only one interrupt for the two edges
detected. The interrupt service routine can read the interrupt pins via Parallel Port E and
determine which lines experienced a transition, provided that the transitions are not too
fast. Interrupts can also be generated by setting up the matching port E bit as an output and
toggling the bit.
Table 7-10. Control Registers for External Interrupts
Reg Name
Reg Address
I0CR
10011000
I1CR
10011001
User's Manual
INT1A [PE1]
pulse
catcher
INT1B [PE5]
pulse
catcher
INT0A [PE0]
pulse
catcher
INT0B [PE4]
pulse
catcher
Figure 7-6. External Interrupt Line Logic
Bits 7,6
xx
xx
#1 interrupt acknowledge
#0 interrupt acknowledge
Bits 5,4
Bits 3,2
INT0B PE4
INT0A PE0
INT1B PE5
INT1A PE1
edge triggered
edge triggered
00-disabled
00-disabled
10-rising
10-rising
01-falling
01-falling
11-both
11-both
Bits 1,0
Enb INT0
Enb INT1
interrupt
00-disable
01-pri 1
10-pri 2
11-pri 3
91
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