6.1 Default Values for all the Peripheral Control Registers
The default values for all of the peripheral control registers are shown in Table 6-2. The
registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter
(PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones
(disabling all interrupts), while all of the other listed CPU registers are reset to all zeros.
Register Name
Breakpoint/Debug Control Register
Global Control/Status Register
Global Clock Modulator 0 Register
Global Clock Modulator 1 Register
Global Clock Double Register
Global Output Control Register
MMU Instruction/Data Register
MMU Common Base Register
MMU Bank Base Register
MMU Common Bank Area Register
Memory Bank 0 Control Register
Memory Bank 1 Control Register
Memory Bank 2 Control Register
Memory Bank 3 Control Register
MMU Expanded Code Register
Memory Timing Control Register
Slave Port Data 0 Register
Slave Port Data 1 Register
Slave Port Data 2 Register
Slave Port Status Register
Slave Port Control Register
Global ROM Configuration Register
Global RAM Configuration Register
Global CPU Configuration Register
Global Revision Register
User's Manual
Table 6-2. Rabbit Internal I/O Registers
Mnemonic
BDCR
GCSR
GCM0R
GCM1R
GCDR
GOCR
MMIDR
STACKSEG
DATASEG
SEGSIZE
MB0CR
MB1CR
MB2CR
MB3CR
MECR
MTCR
SPD0R
SPD1R
SPD2R
SPSR
SPCR
GROM
GRAM
GCPU
GREV
I/O Address
R/W
0x0C
W
0x00
R/W
0x0A
W
0x0B
W
0x0F
W
0x0E
W
0x10
R/W
0x11
R/W
0x12
R/W
0x13
R/W
0x14
W
0x15
W
0x16
W
0x17
W
0x18
R/W
0x19
W
0x20
R/W
0x21
R/W
0x22
R/W
0x23
R
0x24
R/W
0x2C
R
0x2D
R
0x2E
R
0x2F
R
Reset
0xxxxxxx
11000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
11111111
00001000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxx000
xxxx0000
xxxxxxxx
xxxxxxxx
xxxxxxxx
00000000
0xx00000
0xx00000
0xx00000
0xx00001
0xx00000
67
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