7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN
Certain output pins can have alternate assignments as specified in Table 7-4.
Table 7-4. Global Output Control Register (GOCR = 0Eh)
Bit(s)
Value
00
01
7:6
10
11
00
01
5:4
10
11
1
3
0
2
x
00
01
1:0
10
11
User's Manual
CLK pin is driven with peripheral clock.
CLK pin is driven with peripheral clock divided by 2.
CLK pin is low.
CLK pin is high.
STATUS pin is active (low) during a first opcode byte fetch.
STATUS pin is active (low) during an interrupt acknowledge.
STATUS pin is low.
STATUS pin is high.
WDTOUTB pin is low (1 cycle minimum, 2 cycles maximum, of 32 kHz).
WDTOUTB pin follows watchdog function.
This bit is ignored.
/BUFEN pin is active (low) during external I/O cycles.
/BUFEN pin is active (low) during data memory accesses.
/BUFEN pin is low.
/BUFEN pin is high.
Description
83
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