Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual page 16

Lattice Semiconductor
Figure 5 shows the timing waveform for two words DMA transfer.
Figure 5. Two Word DMA Transfer Timing Waveform
Clock
iorout_n/memr_n
iowout_n/memw_n
Note 1. This timing diagram demonstrates the extended write operation. In the 8237 mode, when normal write operation is
selected, iowout_n or the memw_n is asserted one clock cycle later.
If compressed timing is selected, the state S3 is bypassed, making the read and write pulses of equal width. This is only
applicable in 8237 mode.
The iowout_n and memw_n signals are generated off the falling clock edge. This ensures the address is held at least for
half a cycle after the rising edge of the write signal.
Si S0
dreq
hreq
hlda
aen
aout
dack
Multi-Channel DMA Controller User's Guide
S0
S1 S2 S3 S4
Valid Address
Note 1.
16
S2
S3 S4 Si
Valid Address