Timing Specifications - Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual

Lattice Semiconductor
Table 4. Signal Definitions of the MCDMA Controller (Continued)
Port Name
aen
aout [ADDR_BUS_WIDTH-1:0]
dack[N-1:0]
Note: N = number of channels
Timing Specifications
Figure 3 illustrates the waveform for a write operation into one of the internal registers in the MCDMA core. Clock
edges 1, 2 and 3 indicate the point where the data is written into the registers. Clock edges 2 and 3 indicate a back-
to-back write operation into the same register. The iorin_n signal is held high during the entire write operation.
Figure 3. Processor Write Timing Waveform
Figure 4 shows the processor read timing waveform. Data is available on the following clock edge after cs_n and
iorin_n are asserted. Clock edges 1, 2, and 3 indicate the edges on which the data is valid.
Type Active State
Output High
Output N/A
Output High/Low
1
Clock
cs_n
iowin_n
ain
dbin
Multi-Channel DMA Controller User's Guide
Address Enable. This active high signal enables the 8-bit
latch that contains the upper 8 address bits onto the system
address bus.
Address Output. These lines are enabled only during active
DMA transfer and contain the memory address.
DMA Acknowledge. This signal is used to notify the request-
ing peripheral that it has been granted a DMA cycle. The
polarity of this signal is programmable. A device reset initial-
izes all dack signals to active low.
2 3
14
Description