Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual page 25

Lattice Semiconductor
Appendix for ispXPGA
Table 20. Performance and Resource Utilization
Mode Parameter File
8237 dma_mc_xp_2_001.lpc
Non-8237 dma_mc_xp_2_002.lpc
1. Performance and utilization characteristics are generated using LFX1200B-05F900C in Lattice ispLEVER 3.x software. The evaluation ver-
sion of this IP core only works on this specific device density, package, and speed grade.
2. PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
Supplied Netlist Configurations
The Ordering Part Number (OPN) for all configurations of this core in ispXPGA devices is DMA-MC-XP-N2.
Table 21 lists the Lattice-specific netlists that are available in the Evaluation Package, which can be downloaded
from the Lattice web site at www.latticesemi.com.
Table 21. Core Configuration
Name of
Parameter File
8237 Mode
dma_mc_xp_2_001.lpc
Non-8237 Mode
dma_mc_xp_2_002.lpc
You can use the IPexpress software tool to help generate new configurations of this IP core. IPexpress is the Lattice
IP configuration utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the
usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more information on the
ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com/software.
®
FPGAs
Name of
LUT4
1450
3487
Number of Channels
4
4
Multi-Channel DMA Controller User's Guide
1
ispXPGA
2 2
PFUs Registers
432 562
1072 1181
Data Bus Width Address Bus Width
8
32
25
sysMEM
EBRs I/O
N/A 58
N/A 124
Word Count Width
16 16
32 16
f (MHz)
MAX
58
66