Table 3-7. Dma Specifications - HP 330 Service Information Manual

Direct Memory Addressing
DMA chip architecture is a compatible superset of the HP 98620B DMA Controller which is used
with HP 9000 series 200 and 300 computers. The chip is a Standard-Cell design implemented
in a CMOS process.
Refer to Table 3-7 for DMA specifications.
Table 3-7. DMA Specifications
Feature
Input Clock
Channels
Channel Priority
Channel Arbitration
Bus Arbitration
Transfer Types
Max Transfers
Bus Bandwidth Use Limits
Min Cycle Time
Max Theoretical Transfer Rate
Typical Burst Transfer Rate
Interrupt levels
Address range
LAN Interface
Specification
10 MHz
2
Programmable, high or low, each channel
Round-robin
D I 0 daisy chain
8-bit (byte)
16-bit (word)
32-bit (long word)
4G transfers per arming
Programmable: 100%, 50%, 25%, 12.5%
300 ns
13.3 Mbytes/sec
2.8 Mbytes/sec (word transfers to RAM
controller boards
Programmable: 7, 6, 5, 4, 3
FFFFFFFF - 00000000
Local Area Network (LAN) functions are divided into three areas:
• Backplane interface to the DIO-II bus.
• Shared melIlory area.
• Frontplane interface to the network.
Interface with the DIO-II bus includes select code decoding, interrupt control, data bus buffers
and latches, and address multiplexers. A 16-bit wide data bus is used.
The shared memory area has the memory controller circuits, 16 Kbytes of RAM, 64 nybbles
of nonvolatile storage of the node address, and standard DIO control, status, and ID registers.
Multiplexing of DIO-II information and the LAN chip set is also part of the controller circuit.
102
Functional Description