HP 330 Service Information Manual page 106

RAM Address and Size
The address select and autosize block contains ten switches to configure the 4 Mbyte RAM
controller board and add-on board, if attached. Set the switches to locate the top address for
the block. If an add-on board is added, the switches won't change because the autosize circuit
locates the add-on RAM below the 4 Mbyte block on the RAM controller board. 4 Mbyte RAM
controller boards used in the Model 330 must be configured next to the 4 Mbyte block on the
Model 330 processor board, which also has RAM configuration switches.
RAM Clock
The 4 Mbyte RAM controller board is clocked by 25 MHz from the Model 350 through the
system bus and the on-board 25 MHz clock is disabled. In Model 330 computers, the 25 MHz
is generated from a 50 MHz crystal on the RAM controller board.
Board Select
A board select circuit will determine when the board is being accessed and will issue either
system bus select or DIO-II bus select. The RAM block select circuit will determine which 4
Mbyte block is being accessed.
Write Cycle
For a write cycle, after select is issued, the lower address lines will be latched. Then the data
lines are latched, and parity will be generated. Finally, both the data and the parity will be
written to the appropriate RAM chips.
Read Cycles
Normal Read Cycle
For a normal read cycle, after select is issued, the lower address lines will be latched. Then the
appropriate RAM chips will be read and parity will be checked providing parity is enabled. If
there is a parity error, it is indicated to the CPU and data will be latched. If there is no parity
error, the data will be latched to the data bus.
Quad Read Cycle
A cache fill read runs the same as a standard read, except 4 long reads are performed.
Fold Buffer
A fold buffer is used to 'fold' data from the upper 16 data bits to the lower 16 data bits, or
the other way around. This is used when a 16 bit device, such as the DOS or high-speed disc
interface board, accesses data that is stored in 32-bit format.
Control Register
The control register is used to turn on and off parity and to determine if interrupt was caused
by a parity error.
Model 350 System Bus Data Transfers
The dual-ported 4 Mbyte RAM controller board supports a high-speed 32-bit synchronous
system bus port and a 32-bit asynchronous DIO-II port. The DIO-II port also supports DIO
bus masters allowing it to be used with either processor board as well as the HP 98286A DOS
Coprocessor System.
90 Functional Description