Status Byte Register - Keithley 2280 Series Reference Manual

Appendix D: Status model

Status Byte Register

The Status Byte Register consists of two 8-bit registers that control service requests, the Status Byte
Register, and the Service Request Enable Register. These summary bits do not latch, and their
states (0 or 1) are solely dependent on the summary messages (0 or 1). For example, if the Standard
Event Register is read, its register will clear. As a result, its summary message will reset to 0, which
then will reset the ESB bit in the Status Byte Register. These registers are shown in the following
figure.
The bits of the Status Byte Register are described in the following table:
Decimal
Bit value
0
1
2
3
4
5
6
7 128
D-6
Series 2280 Precision Measurement DC Power Supplies Reference Manual
Figure 129: Series 2280 Status Byte Register
Bit name
1 Measurement summary bit (MSB)
2 Not used
4 Error available (EAV)
8 Questionable summary bit (QSB)
16 Message available (MAV)
32 Event summary bit (ESB)
64 Request for service (RQS)/Master summary
status (MSS)
Operation summary bit (OSB)
When set, indicates the following
has occurred:
An enabled measurement event
Not applicable
An error is present in the error queue
(warning and information messages do
not affect this bit)
An enabled questionable event
A response message is present in the
output queue
An enabled standard event
An enabled summary bit of the Status
Byte Register is set; depending on
how it is used, this is either the
Request for Service (RQS) bit or the
Master Summary Status (MSS) bit
An enabled operation event
077085501 / February 2015