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Renesas V850ES/JF3-E User Manual (1633 pages)

Brand: Renesas | Category: Microcontrollers | Size: 8 MB

Index
4
Table of Contents
8
Chapter 1 Introduction

21
- General
  21
- Features
  25
- Application Fields
  27
- Ordering Information
  27
- Pin Configuration (Top View)
  28
- Function Block Configuration
  33
- Internal Block Diagram
  33
- Internal Units
  36
Chapter 2 Pin Functions

39
Chapter 3 Cpu Function

54
- Features
  54
- CPU Register Set
  55
- Program Register Set
  56
- System Register Set
  57
- Operation Modes
  63
- Specifying Operation Mode
  63
- Address Space
  64
- CPU Address Space
  64
- Wraparound of CPU Address Space
  65
- Memory Map
  66
- Areas
  69
- Recommended Use of Address Space
  74
- Peripheral I/O Registers
  77
- Programmable Peripheral I/O Registers
  90
- Special Registers
  91
- Cautions
  95
Chapter 4 Port Functions

99
- Features
  99
- Basic Port Configuration
  99
- Port Configuration
  101
- Port 0
  107
- Port 2
  111
- Port 3
  119
- Port 4
  129
- Port 5
  136
- Port 7
  139
- Port 9 (V850ES/JF3-E, V850ES/JG3-E)
  141
- Port DL
  152
- Port Register Settings When Alternate Function Is Used
  154
- Cautions
  163
- Cautions on Setting Port Pins
  163
- Cautions on Bit Manipulation Instruction for Port N Register (Pn)
  166
- Cautions on On-Chip Debug Pins
  167
- Cautions on P54/INTP11/DRST Pin
  167
- Cautions on P51 Pin When Power Is Turned on
  167
- Hysteresis Characteristics
  167
Chapter 5 Clock Generation Function

168
- Overview
  168
- Configuration
  169
- Registers
  171
- Operation
  176
- Operation of each Clock
  176
- PLL Function
  177
- Overview
  177
- Registers
  177
- Usage
  180
Chapter 6 16-Bit Timer/Event Counter Aa (Taa)

181
- Overview
  181
- Functions
  181
- Configuration
  182
- Pin Configuration
  184
- Register Configuration
  185
- Registers
  188
- Operation
  205
- Interval Timer Mode (Taanmd2 to Taanmd0 Bits = 000)
  212
- External Event Count Mode (Taanmd2 to Taanmd0 Bits = 001)
  222
- External Trigger Pulse Output Mode (Taanmd2 to Taanmd0 Bits = 010)
  230
- One-Shot Pulse Output Mode (Taanmd2 to Taanmd0 Bits = 011)
  242
- PWM Output Mode (Taanmd2 to Taanmd0 Bits = 100)
  249
- Free-Running Timer Mode (Taanmd2 to Taanmd0 Bits = 101)
  258
- Pulse Width Measurement Mode (Taanmd2 to Taanmd0 Bits = 110)
  275
- Timer Output Operations
  280
- Timer-Tuned Operation Function
  281
- Free-Running Timer Mode (During Timer-Tuned Operation)
  283
- PWM Output Mode (During Timer-Tuned Operation)
  290
- Simultaneous-Start Function
  292
- PWM Output Mode (Simultaneous-Start Operation)
  293
- Cascade Connection
  295
- Selector Function
  300
- Cautions
  301
Chapter 7 16-Bit Timer/Event Counter Ab (Tab)

302
Chapter 8 16-Bit Timer/Event Counter T (Tmt)

407
Chapter 9 16-Bit Interval Timer M (Tmm)

540
- Overview
  540
- Configuration
  541
- Registers
  543
- Operation
  545
- Interval Timer Mode
  545
- Cautions
  549
Chapter 10 Motor Control Function

550
- Functional Overview
  550
- Configuration
  551
- Control Registers
  555
- Operation
  565
- System Outline
  565
- Dead-Time Control (Generation of Negative-Phase Wave Signal)
  570
- Interrupt Culling Function
  576
- Operation to Rewrite Register with Transfer Function
  584
- TAA4 Tuning Operation for A/D Conversion Start Trigger Signal Output
  602
- A/D Conversion Start Trigger Output Function
  605
Chapter 11 Real-Time Counter

610
Chapter 12 Functions of Watchdog Timer 2

641
- Functions
  641
- Configuration
  642
- Registers
  643
- Operation
  645
Chapter 13 Real-Time Output Function (Rto)

646
- Function
  646
- Configuration
  647
- Registers
  649
- Operation
  651
- Usage
  652
- Cautions
  652
Chapter 14 A/D Converter

653
- Overview
  653
- Functions
  653
- Configuration
  654
- Registers
  657
- Operation
  668
- Basic Operation
  668
- Conversion Operation Timing
  669
- Trigger Mode
  670
- Operation Mode
  672
- Power-Fail Compare Mode
  676
- Cautions
  681
- How to Read A/D Converter Characteristics Table
  685
Chapter 15 Asynchronous Serial Interface C (Uartc)

689
- Features
  689
- Configuration
  690
- Mode Switching between UARTC and Other Serial Interfaces
  692
- Mode Switching between UARTC0 and CSIF2
  692
- Mode Switching between UARTC1, CSIF1 and I 2 C00
  693
- C02, and CAN0
  694
- Mode Switching between UARTC3, CSIF0, and I 2 C01
  695
- Registers
  696
- Interrupt Request Signals
  706
- Operation
  707
- Data Format
  707
- SBF Transmission/Reception Format
  709
- SBF Transmission
  711
- SBF Reception
  712
- UART Transmission
  713
- Continuous Transmission Procedure
  714
- UART Reception
  716
- Reception Errors
  718
- Parity Types and Operations
  720
- Receive Data Noise Filter
  721
- Dedicated Baud Rate Generator
  722
- Cautions
  731
Chapter 16 Clocked Serial Interface F (Csif)

732
Chapter 17 I C Bus

784
- Features
  784
- Configuration
  785
- C Bus and Other Serial Interfaces
  789
- C00, CSIF1, and UARTC1
  789
- C01, CSIF0, and UARTC3
  790
- C02, UARTC2, and CAN0
  791
- Registers
  792
- I C Bus Mode Functions
  807
- Pin Configuration
  807
- I C Bus Definitions and Control Methods
  808
- Start Condition
  809
- Addresses
  810
- Transfer Direction Specification
  811
- Ack
  812
- Stop Condition
  813
- Wait State
  814
- Wait State Cancellation Method
  816
- I C Interrupt Request Signals (Intiicn)
  817
- Master Device Operation
  817
- Slave Device Operation (When Receiving Slave Address Data (Address Match))
  820
- Slave Device Operation (When Receiving Extension Code)
  824
- Operation Without Communication
  827
- Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
  828
- Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
  830
- Interrupt Request Signal (Intiicn) Generation Timing and Wait Control
  837
- Address Match Detection Method
  839
- Error Detection
  839
- Extension Code
  839
- Arbitration
  840
- Wakeup Function
  841
- Communication Reservation
  842
- When Communication Reservation Function Is Enabled (Iicfn.iicrsvn Bit = 0)
  842
- When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
  846
- Cautions
  847
- Communication Operations
  848
- Master Operation in Single Master System
  849
- Master Operation in Multimaster System
  850
- Slave Operation
  853
- Timing of Data Communication
  857
Chapter 18 Can Controller

864
- Overview
  864
- Features
  864
- Overview of Functions
  865
- Configuration
  866
- CAN Protocol
  867
- Frame Format
  867
- Frame Types
  868
- Data Frame and Remote Frame
  868
- Error Frame
  876
- Overload Frame
  877
- Functions
  878
- Determining Bus Priority
  878
- Bit Stuffing
  878
- Multi Masters
  878
- Multi Cast
  878
- CAN Sleep Mode/Can Stop Mode Function
  879
- Error Control Function
  879
- Baud Rate Control Function
  886
- Connection with Target System
  890
- Internal Registers of CAN Controller
  891
- CAN Controller Configuration
  891
- Register Access Type
  892
- Register Bit Configuration
  909
- Registers
  913
- Bit Set/Clear Function
  949
- CAN Controller Initialization
  951
- Initialization of CAN Module
  951
- Initialization of Message Buffer
  951
- Redefinition of Message Buffer
  951
- Transition from Initialization Mode to Operation Mode
  952
- Resetting Error Counter C0ERC of CAN Module
  953
- Message Reception
  954
- Reading Reception Data
  955
- Receive History List Function
  956
- Mask Function
  958
- Multi Buffer Receive Block Function
  960
- Remote Frame Reception
  961
- Message Transmission
  962
- Transmit History List Function
  964
- Automatic Block Transmission (ABT)
  966
- Transmission Abort Process
  968
- Remote Frame Transmission
  969
- Power Saving Modes
  970
- CAN Sleep Mode
  970
- CAN Stop Mode
  972
- Example of Using Power Saving Modes
  973
- Interrupt Function
  974
- Diagnosis Functions and Special Operational Modes
  975
- Receive-Only Mode
  975
- Single-Shot Mode
  976
- Self-Test Mode
  977
- Transmission/Reception Operation in each Operation Mode
  978
- Time Stamp Function
  979
- Baud Rate Settings
  981
- Bit Rate Setting Conditions
  981
- Representative Examples of Baud Rate Settings
  985
- Operation of CAN Controller
  989
Chapter 19 Usb Function Controller (Usbf)

1015
- Overview
  1015
- Configuration
  1016
- Block Diagram
  1016
- USB Memory Map
  1017
- External Circuit Configuration
  1018
- Outline
  1018
- Connection Configuration
  1019
- Cautions
  1021
- Requests
  1022
- Automatic Requests
  1022
- Other Requests
  1029
- Register Configuration
  1030
- USB Control Registers
  1030
- External Bus Control Registers
  1032
- USB Function Controller Register List
  1035
- EPC Control Registers
  1051
- Data Hold Registers
  1103
- EPC Request Data Registers
  1126
- Bridge Register
  1141
- DMA Register
  1145
- Peripheral Control Registers
  1149
- STALL Handshake or no Handshake
  1153
- Register Values in Specific Status
  1154
- FW Processing
  1156
- Initialization Processing
  1158
- Interrupt Servicing
  1161
- USB Main Processing
  1162
- Suspend/Resume Processing
  1188
- Processing after Power Application
  1191
- Receiving Data for Bulk Transfer (OUT) in DMA Mode
  1194
- Transmitting Data for Bulk Transfer (IN) in DMA Mode
  1199
Chapter 20 Ethernet Controller

1204
- General
  1204
- Functions
  1204
- Configuration
  1205
- System Configuration
  1205
- Interrupt Requests
  1206
- Initialization
  1206
- Registers for Controlling the Ethernet Controller
  1209
- MAC Control Registers
  1213
- Statistics Counters
  1243
- FIFO Controller Control Registers
  1282
- DMAC Control Registers in Ethernet Controller
  1309
- MAC/FIFO/DMAC Function
  1319
- Frame Format
  1319
- Transmit Function
  1322
- Receive Function
  1326
- MAC Control Function
  1328
- Dedicated DMAC
  1332
- Serial Management Interface
  1334
- Address Filtering
  1338
- Statistics Counters
  1343
- Data Transmission
  1344
- Buffer Structure
  1344
- Descriptor Mechanism
  1346
- Frame Transmission
  1355
- Frame Reception
  1360
- Error Occurrence
  1365
- Receive Checksum
  1366
- Processing by Software
  1366
- Notes
  1368
- Notes on FIFO
  1368
Chapter 21 Dma Function (Dma Controller)

1369
- Features
  1369
- Configuration
  1370
- Registers
  1371
- Transfer Targets
  1379
- Transfer Modes
  1379
- Transfer Types
  1380
- DMA Channel Priorities
  1381
- Time Related to DMA Transfer
  1381
- DMA Transfer Start Factors
  1382
- End of DMA Transfer
  1383
- Cautions
  1383
Chapter 22 Interrupt/Exception Processing Function

1387
- Features
  1387
- Non-Maskable Interrupts
  1399
- Operation
  1401
- Restore
  1402
- NP Flag
  1403
- Maskable Interrupts
  1404
- Operation
  1404
- Restore
  1406
- Priorities of Maskable Interrupts
  1407
- Interrupt Control Register (Xxicn)
  1411
- Interrupt Mask Registers 0 to 7 (IMR0 to IMR7)
  1415
- In-Service Priority Register (ISPR)
  1417
- ID Flag
  1418
- Watchdog Timer Mode Register 2 (WDTM2)
  1418
- Software Exception
  1419
- Operation
  1419
- Restore
  1420
- EP Flag
  1421
- Exception Trap
  1422
- Illegal Opcode
  1422
- Debug Trap
  1424
- External Interrupt Request Input Pins (NMI and Intpn)
  1426
- Noise Elimination
  1426
- Edge Detection
  1426
- Interrupt Acknowledge Time of CPU
  1433
- Periods in Which Interrupts Are Not Acknowledged by CPU
  1434
- Cautions
  1434
CHAPTER 23 KEY INTERRUPT FUNCTION (V850ES/JE3-E and V850ES/JG3-E)

1435
- Function
  1435
- Register
  1436
- Cautions
  1436
Chapter 24 Standby Function

1437
- Overview
  1437
- Registers
  1439
- HALT Mode
  1442
- Setting and Operation Status
  1442
- Releasing HALT Mode
  1442
- IDLE1 Mode
  1444
- Setting and Operation Status
  1444
- Releasing IDLE1 Mode
  1445
- IDLE2 Mode
  1447
- Setting and Operation Status
  1447
- Releasing IDLE2 Mode
  1448
- Securing Setup Time When Releasing IDLE2 Mode
  1450
- STOP Mode
  1451
- Setting and Operation Status
  1451
- Releasing STOP Mode
  1451
- Securing Oscillation Stabilization Time When Releasing STOP Mode
  1454
- Subclock Operation Mode
  1455
- Setting and Operation Status
  1455
- Releasing Subclock Operation Mode
  1455
- Sub-IDLE Mode
  1457
- Setting and Operation Status
  1457
- Releasing Sub-IDLE Mode
  1457
Chapter 25 Reset Functions

1460
- Overview
  1460
- Registers to Check Reset Source
  1461
- Operation
  1462
- Reset Operation Via RESET Pin
  1462
- Reset Operation by Watchdog Timer 2
  1464
- Reset by Clock Monitor
  1466
- Reset Operation by Low-Voltage Detector
  1467
- Operation after Reset Release
  1468
- Reset Function Operation Flow
  1469
Chapter 26 Clock Monitor

1470
- Functions
  1470
- Configuration
  1470
- Register
  1471
- Operation
  1472
Chapter 27 Low-Voltage Detector (Lvi)

1475
- Functions
  1475
- Configuration
  1475
- Registers
  1476
- Operation
  1478
- To Use for Internal Reset Signal
  1478
- To Use for Interrupt
  1479
- RAM Retention Voltage Detection Operation
  1480
Chapter 28 Crc Function

1481
- Functions
  1481
- Configuration
  1481
- Registers
  1482
- Operation
  1483
- Usage Method
  1484
Chapter 29 Regulator

1486
- Overview
  1486
- Operation
  1487
Chapter 30 Flash Memory

1488
- Features
  1488
- Memory Configuration
  1489
- Functional Overview
  1490
- Rewriting by Dedicated Flash Programmer
  1493
- Programming Environment
  1493
- Communication Mode
  1494
- Flash Memory Control
  1507
- Selection of Communication Mode
  1508
- Communication Commands
  1509
- Pin Connection
  1510
- Rewriting by Self Programming
  1514
- Overview
  1514
- Features
  1515
- Standard Self Programming Flow
  1516
- Flash Functions
  1517
- Pin Processing
  1517
- Internal Resources Used
  1518
Chapter 31 On-Chip Debug Function

1519
- Debugging with DCU
  1520
- Connection Circuit Example
  1520
- Interface Signals
  1520
- Maskable Functions
  1522
- Register
  1522
- Operation
  1524
- Cautions
  1524
- Debugging Without Using DCU
  1525
- Circuit Connection Examples
  1526
- Maskable Functions
  1530
- Securement of User Resources
  1531
- Cautions
  1538
- ROM Security Function
  1539
- Security ID
  1539
- Setting
  1540
Chapter 32 Electrical Specifications

1542
- Absolute Maximum Ratings
  1542
- Capacitance
  1544
- Operating Conditions
  1544
- Oscillator Characteristics
  1545
- Main Clock Oscillator Characteristics
  1545
- Subclock Oscillator Characteristics
  1546
- PLL Characteristics
  1547
- Internal Oscillator Characteristics
  1547
- DC Characteristics
  1548
- I/O Level
  1548
- Supply Current
  1550
- Data Retention Characteristics
  1551
- AC Characteristics
  1552
- Basic Operation
  1553
- Flash Memory Programming Characteristics
  1567
Chapter 33 Package Drawings

1568
Chapter 34 Recommended Soldering Conditions

1571
Appendix A Development Tools

1573
- Software Package
  1575
- Language Processing Software
  1575
- Control Software
  1575
- Debugging Tools (Hardware)
  1576
- When Using IECUBE QB-V850ESJX3E
  1576
- When Using MINICUBE QB-V850MINI
  1578
- When Using MINICUBE2 QB-MINI2
  1579
- Debugging Tools (Software)
  1580
- Embedded Software
  1581
- Flash Memory Writing Tools
  1581
Appendix B Register Index

1582
Appendix C Instruction Set List

1620
- Conventions
  1620
- Instruction Set (in Alphabetical Order)
  1623

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Renesas V850ES/JF3-E Manuals

Renesas V850ES/JF3-E User Manual (1633 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Clock Generation Function

Chapter 6 16-Bit Timer/Event Counter Aa (Taa)

Chapter 7 16-Bit Timer/Event Counter Ab (Tab)

Chapter 8 16-Bit Timer/Event Counter T (Tmt)

Chapter 9 16-Bit Interval Timer M (Tmm)

Chapter 10 Motor Control Function

Chapter 11 Real-Time Counter

Chapter 12 Functions of Watchdog Timer 2

Chapter 13 Real-Time Output Function (Rto)

Chapter 14 A/D Converter

Chapter 15 Asynchronous Serial Interface C (Uartc)

Chapter 16 Clocked Serial Interface F (Csif)

Chapter 17 I C Bus

Chapter 18 Can Controller

Chapter 19 Usb Function Controller (Usbf)

Chapter 20 Ethernet Controller

Chapter 21 Dma Function (Dma Controller)

Chapter 22 Interrupt/Exception Processing Function

CHAPTER 23 KEY INTERRUPT FUNCTION (V850ES/JE3-E and V850ES/JG3-E)

Chapter 24 Standby Function

Chapter 25 Reset Functions

Chapter 26 Clock Monitor

Chapter 27 Low-Voltage Detector (Lvi)

Chapter 28 Crc Function

Chapter 29 Regulator

Chapter 30 Flash Memory

Chapter 31 On-Chip Debug Function

Chapter 32 Electrical Specifications

Chapter 33 Package Drawings

Chapter 34 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Register Index

Appendix C Instruction Set List

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