Maverick EP7312 User Manual page 80

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Bit
16-21
RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last incre-
ment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down
to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.
22
URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the RX holding register is empty. If the FIFO is enabled, the URXFE bit will be set when the
RX FIFO is empty.
23
UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX
FIFO is full.
24
CRXFE: CODEC RX FIFO empty bit. This will be set if the 16-byte CODEC RX FIFO is empty.
25
CTXFF: CODEC TX FIFO full bit. This will be set if the 16-byte CODEC TX FIFO is full.
26
SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in
or out of the synchronous serial interface, when clear data is valid to read.
27-28
BOOTBIT[0-1]: These bits indicate the default (power-on reset) bus width of the ROM interface.
See Memory Configuration Registers for more details on the ROM interface bus width. The state
of these bits reflect the state of Port E[0-1] during power on reset, as shown in the table below.
29
ID: Will always read "1" for the EP7312 device
30-31
VERID: Version ID bits. These 2 bits determine the version ID for the EP7312. Will read "01" for
the initial version.
DS508UM1
Description
PE[1]
PE[0]
(BOOTBIT1)
(BOOTBIT0)
0
0
1
1
Table 38. SYSFLG1 (cont.)
Boot Option
0
32-bit
1
8-bit
0
16-bit
1
Reserved
81

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