Maverick EP7312 User Manual page 70

Address Name
0x8000.1700 KBDEOI
0x8000.1800 Reserved
0x8000.1840 Reserved
–
0x8000.1FFF
0x8000.2000 DAIR
0x8000.2040 DAIR0
0x8000.2080 DAIDR1
0x8000.20C0 DAIDR2
0x8000.2100 DAISR
0x8000.2200 SYSCON3
0x8000.2240 INTSR3
0x8000.2280 INTMR3
LEDFLSH
0x8000.22C0
0x8000.2300 SDCONF*
0x8000.2340 SDRFPR*
0x8000.2440 UNIQID*
0x8000.2700 RANDID0*
0x8000.2704 RANDID1*
0x8000.2708 RANDID2*
0x8000.270C RANDID3*
0x8000.8000 Reserved
BFFF.FFFF
DAI64Fs*
0x8000.2600
* Internal registers that are not backward compatible with the EP72XX.
DS508UM1
Default RD/WR
— WR
— WR
—
0 RW
0 RW
0 RW
0 WR
0 RW
0 RW
0 RD
0 RW
0 RW
2 RW
128 RW
0 R
0 R
0 R
0 R
0 R
0 RW
0 RW
Table 33. EP7312 Internal Registers (Little Endian Mode) (cont.)
Size
— Write to clear keyboard interrupt
— Do not write to this location. A write will cause
the
processor to go into an unsupported power
savings state.
Write will have no effect, read is undefined
32 DAI control register
32 DAI data register 0
32 DAI data register 1
21 DAI data register 2
32 DAI status register
16 System control register 3
32 Interrupt status register 3
8 Interrupt mask register 3
7 LED Flash register
32 SDRAM Configuration Register
16 SDRAM Refresh Register
32 32-bit unique ID for the EP7312 device
32 Bits 31-0 of 128-bit random ID for the EP7312
device
32 Bits 63-32 of 128-bit random ID for the EP7312
device
32 Bits 95-64 of 128-bit random ID for the EP7312
device
32 Bits 127-96 of 128-bit random ID for the
EP7312 device
32 This area contains test register used during
manufacturing test. Writes to this area should
never be attempted during normal operation as
this may cause unexpected behavior. Any read
from this register will be undefined.
32 DAI 64Fs Control Register
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