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Function
Signal
Name
PA[0-7]
PB[0] / PRDY1
General
PB[1] / PRDY2
Purpose I/O
PB[2-7]
PD[0-5]
PD[6-7]/ SDQM
[0-1]
PE[0]/
BOOTSEL[0]
PE[1] /
BOOTSEL[1]
PE[2 ]/
CLKSEL
DRIVE[0-1]
PWM
Drives
FB[0-1]
TDI
TDO
TMS
Boundary
Scan
TCLK
nTRST
Test
nTEST[0-1]
MOSCIN
MOSCOUT
Oscillators
RTCIN
RTCOUT
No Connects
N/C
All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least
two clock periods. Therefore, the input signal must be active for at least ~125 µs to be detected cleanly.
Note:
The RTC crystal must be populated for the device to function properly.
DS508UM1
Signal
I/O
Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY
input); also used as keyboard row inputs
I/O
Port B I/O. All eight Port B bits can be used as GPIOs.
When the PC CARD1 or 2 control bits in the SYSCON2 register are
de-asserted, PB[0] and PB[1] are available for GPIO. When asserted,
these port bits are used as the PRDY signals for connected CL-
PS6700 PC Card Host Adapter devices.
I/O
Port D I/O
I/O
Port D I/O, byte mask select.
I/O
Port E I/O (3 bits only). Can be used as general purpose I/O during
normal operation.
I/O
During power-on reset, PE[0] and PE[1] are inputs and are latched by
the rising edge of nPOR to select the memory width that the EP7312
will use to read from the boot code storage device (i.e., external 8-bit-
wide FLASH bank).
I/O
During power-on reset, PE[2] is latched by the rising edge of nPOR to
select the clock mode of operation (i.e., either the PLL or external 13
MHz clock mode).
I/O
PWM drive outputs. These pins are inputs on power up to determine
what polarity the output of the PWM should be when active. Otherwise,
these pins are always an output (See Table 31 on page 66).
I
PWM feedback inputs
I
JTAG data in
O
JTAG data out
I
JTAG mode select
I
JTAG clock
I
JTAG async reset
I
Test mode select inputs. These pins are used in conjunction with the
power-on latched state of nURESET to select between the various
device test models.
I
Main 3.6864 MHz oscillator for 18.432 MHz–73.728 MHz PLL
O
I
Real Time Clock 32.768 kHz oscillator
O
No connects should be left as no connects; do not connect to ground
Table 29. External Signal Functions (cont.)
Description
65
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