Maverick EP7312 User Manual page 74

Bit
9 BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is
selected (i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ (SYSCON1) bits for more
details.
10 BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin
is connected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer
drive is in the hardware mode. Two hardware sources are available to drive the pin. They are the
TC1 or a fixed internally generated clock source. The selection of which source is used to drive
the pin is determined by the state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is
selected, then the buzzer output pin is connected to the TC1 under flow bit. The buzzer output
pin changes every time the timer wraps around. The frequency depends on what was pro-
grammed into the timer. See the description of the BUZFREQ and BZTOG bits (SYSCON2) for
more details.
11 DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are out-
put as if they were reads or writes to the expansion memory addressed by nCS5. nCS5 will still
be active in its standard address range. In addition, the internal interrupt request and fast inter-
rupt request signals to the ARM720T processor are output on Port E, bits 1 and 2. Note that
these bits must be programmed to be outputs before this functionality can be observed. The
clock to the CPU is output on Port E, Bit 0 to delineate individual accesses. For example, in
debug mode:
12 LCDEN: LCD enable bit. Setting this bit enables the LCD controller.
13 CDENTX: CODEC interface enable TX bit. Setting this bit enables the CODEC interface for data
transmission to an external CODEC device.
14 CDENRX: CODEC interface enable RX bit. Setting this bit enables the CODEC interface for data
reception from an external CODEC device.
NOTE: Both CDENRX and CDENTX need to be enabled / disabled in tandem, otherwise data may
be lost.
15 SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not
enabled.
16-17 ADCKSEL: Microwire / SPI peripheral clock speed select. This two-bit field selects the frequency
of the ADC sample clock, which is twice the frequency of the synchronous serial ADC interface
clock. The table below shows the available frequencies for operation when in PLL mode. These
bits are also used to select the shift clock frequency for the SSI2 interface when set into master
mode. The frequencies obtained in 13.0 MHz mode can be found in Table 1 on page 10.
DS508UM1
nCS5 = nCS5 or internal I/O strobe
ADCKSEL ADC Sample Frequency
(kHz) — SMPCLK
00
01
10
11
Table 35. SYSCON1 (cont.)
Description
PE0 = CLK
PE1 = nIRQ
PE2 = nFIQ
ADC Clock Frequency
8
32
128
256
(kHz) — ADCCLK
4
16
64
128
75