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Maverick EP7312 User Manual

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EP7312
User's Manual
EP7312 USER'S MANUAL
Copyright © 2000– Cirrus Logic Inc. All Rights Reserved.
Note: Cirrus Logic assumes no responsibility for the attached information which is provided
"AS IS" without warranty of any kind (expressed or implied).
Copyright © Cirrus Logic, Inc. 2000
P.O. Box 17847, Austin, Texas 78760
SEPT '00
(512) 445 7222 FAX: (512) 445 7581
(All Rights Reserved)
DS508UM1
http://www.cirrus.com
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  • Page 1 EP7312 User’s Manual EP7312 USER’S MANUAL Copyright © 2000– Cirrus Logic Inc. All Rights Reserved. Note: Cirrus Logic assumes no responsibility for the attached information which is provided “AS IS” without warranty of any kind (expressed or implied). Copyright © Cirrus Logic, Inc. 2000 P.O.

  • Page 2: Table Of Contents

    1.1 Acronyms and Abbreviations .................... 10 1.2 Units of Measurement ...................... 11 1.3 General Conventions ......................12 1.4 Pin Description Conventions ..................... 12 2. EP7312 FUNCTIONAL DESCRIPTION ................. 13 2.1 CPU Core .......................... 14 2.2 State Control ........................15 2.2.1 Standby State ......................15 2.2.1.1 UART in Standby State ................
  • Page 3 2.21 Boundary Scan ........................ 52 2.22 In-Circuit Emulation ......................53 2.22.1 Introduction ......................53 2.22.2 Functionality ......................53 2.23 Maximum-Configured EP7312-Based System ..............53 2.24 I/O Buffer Characteristics ....................55 3. TEST MODES ......................... 56 3.1 Oscillator and PLL Bypass Mode ..................56 3.2 Oscillator and PLL Test Mode ...................
  • Page 4 6.3.3 INTSR2 — Interrupt Status Register 2 ..............85 6.3.4 INTMR2 — Interrupt Mask Register 2 ..............85 6.3.5 INTSR3 — Interrupt Status Register 3 ..............86 6.3.6 INTMR3 — Interrupt Mask Register 3 ..............86 6.4 Memory Configuration Registers ..................86 6.4.1 MEMCFG1 —...
  • Page 5 Figure 6. Portion of the EP7312 Block Diagram Showing Multiplexed Feature ......40 Figure 7. Digital Audio Clock Generation ..................42 Figure 8. EP7312 Rev B- Digital Audio Interface Timing – MSB / Left Justified format ....43 Figure 9. SSI2 Port Directions in Slave and Master Mode ............45 Figure 10.
  • Page 6 Table 30. SSI/CODEC/DAI Pin Multiplexing ................. 66 Table 31. Output Bi-Directional Pins ..................... 66 Table 32. EP7312 Memory Map in External Boot Mode ............... 67 Table 33. EP7312 Internal Registers (Little Endian Mode) ............69 Table 34. EP7312 Internal Registers (Big Endian Mode) ............. 72 Table 35.
  • Page 7 Table 54. Grayscale Value to Color Mapping................100 Table 55. SYNCIO........................102 Table 56. DAI Control Register ....................106 Table 57. DAI64Fs Control Register ................... 109 Table 58. Clock Source for 64 fs and 128 fs ................109 Table 59. DAI Data Register 0 ....................110 Table 60.

  • Page 8: Part I: Ep7312 User's Manual

    Part I: EP7312 User’s Manual DS508UM1...

  • Page 9: Conventions

    1. CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 1 lists abbreviations and acronyms used in Acronym/ Definition this data sheet. Abbreviation LQFP low profile quad flat pack Acronym/ Definition Abbreviation...

  • Page 10: Units Of Measurement

    Units of Measurement Symbol Unit of Measure ° degree Celsius sample frequency hertz (cycle per second) kbits/s kilobits per second kbyte kilobyte (1,024 bytes) kilohertz kΩ kilohm Mbits/s megabits (1,048,576 bits) per second Mbyte megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) µA microampere µF...

  • Page 11: General Conventions

    General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are en- closed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers not indicated by an “h,”...

  • Page 12: Ep7312 Functional Description

    2. EP7312 FUNCTIONAL DESCRIPTION The EP7312 device is a single-chip embedded controller designed to be used in low-cost and ultra-low- power applications. Operating at 74 MHz, the EP7312 delivers approximately 66 Dhrystone 2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC.

  • Page 13: Cpu Core

    A simplified block diagram of the EP7312 is shown in Figure 1. All external memory and peripheral de- vices are connected to the 32-bit data bus using the external 28-bit address bus and control signals. CPU Core The ARM720T consists of an ARM7TDMI 32-bit RISC processor, a unified cache, and a memory man- agement unit (MMU).

  • Page 14: State Control

    Real Time Clock and its associated logic powered. It is important when the EP7312 is in Standby that all power and ground pins remain connected to power and ground in order to have a proper system wake-up. The only state that Standby can transition to is the Operating State.

  • Page 15: Table 4. Peripheral Status In Different Power States

    When first powered, or reset by the nPOR (Power On Reset, active low) signal, the EP7312 is forced into the Standby State. This is known as a cold reset, and when leaving the Standby State after a cold reset, external wake up is the only way to wake up the device. When leaving the Standby State after non-cold reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Oper-...

  • Page 16: Uart In Standby State

    From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running, the EP7312 will be initialized into a state where it is ready to start and is waiting for the CPU to start re- ceiving its clock.

  • Page 17: Keyboard Interrupt

    2) After nPOR goes HIGH, the EP7312 will enter the Standby State (and only this state). In this state, the PLL is not enabled, and thus the CPU is not enabled either. The only method that can be used to allow the EP7312 to exit the Standby State into the Operating State is by the WAKEUP signal going active (HIGH).

  • Page 18: Resets

    RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved through a user reset or power fail condition. Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7312 returns to the Operating State.

  • Page 19: Clocks

    Clocks There are two clocking modes for the EP7312. Either an external clock input can be used or the on-chip PLL. The clock source is selected by a strapping option on Port E, pin 2 (PE[2]). If PE[2] is high at the rising edge of nPOR (i.e., upon power-up), the external clock mode is selected.

  • Page 20: External Clock Input (13 Mhz)

    External Clock Input (13 MHz) An external 13 MHz crystal oscillator can be used to drive all of the EP7312. When selected the ARM720T and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode.

  • Page 21: Dynamic Clock Switching When In The Pll Clocking Mode

    Table 5 shows the priority order of all the exceptions. The EP7312 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources.

  • Page 22: Table 6. Interrupt Allocation For The First Interrupt Register

    All other interrupt sources (i.e., external interrupt source) must be held active until its respective service routine starts executing. See “End Of Interrupt Locations” for more details. Table 6, Table 7, and Table 8 show the names and allocation of interrupts in the EP7312. Interrupt...

  • Page 23: Interrupt Latencies In Different States

    First, there is a one to two clock cycle syn- chronization penalty. For the case where the EP7312 is operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one wait state FLASH memory, the worst-case interrupt latency is 251 clock cycles.

  • Page 24: Table 9. External Interrupt Sources

    Whenever the EP7312 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are power-down from draining current.

  • Page 25: Ep7312 Boot Rom

    CS[0] (normal boot mode). If nMEDCHG is low, then the boot will be from the on- chip ROM. Note that in both cases, following the de-assertion of power on reset, the EP7312 will be in the Standby State and requires a low-to-high transition on the external WAKEUP pin in order to actually start the boot sequence.

  • Page 26: Memory And I/O Expansion Interface

    Memory and I/O Expansion Interface Six separate linear memory or expansion segments are decoded by the EP7312, two of which can be re- served for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size.

  • Page 27: Sdram Controller

    SDRAM Controller The SDRAM controller in the EP7312 provides all the signals to directly interface to up to four internal banks of SDRAM, and the width of the memory interface is programmable from 16- to 32-bits wide. All internal banks have to be of the same width. The four internal banks that are supported can total together no more than 256 Mbits in size.

  • Page 28: Table 12. Sdram Configurations (Sdram 32-Bit Memory Interface)

    Arrangement of SDRAMs SDRAM Details (C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs) 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes Den- Width sity (bits) (Mbits) Table 12. SDRAM Configurations (SDRAM 32-Bit Memory Interface) DS508UM1...

  • Page 29: Table 13. Sdram Configurations (Sdram 16-Bit Memory Interface)

    Arrangement of SDRAMs SDRAM Details (C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs) 2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes Den- Width sity (bits) (Mbits) 128. 256.

  • Page 30: Sdram Initialization

    SDRAM Address Pins EP7312 Pin Names A27/DRA0 A26/DRA1 A25/DRA2 A24/DRA3 A23/DRA4 A22/DRA5 A21/DRA6 A20/DRA7 A19/DRA8 A18/DRA9 A17/DRA10 A16/DRA11 A15/DRA12 A14/DRA13 A13/DRA14 Table 14. SDRAM Address Pin Connections 2.10 SDRAM Initialization The SDRAM is initialized in the power-on sequence as follows: 1) To stabilize internal circuits when power is applied, a 200 ms pause (or longer) must precede any signal toggling.

  • Page 31: Cl-Ps6700 Pc Card Controller Interface

    10 bits of the PC Card address, along with 6 bits of size, space, and slot infor- mation are put out onto the lower 16 bits of the EP7312’s data bus. Only word (i.e., 4-byte) and single-byte accesses are supported, and the slot field is hardcoded to 11, since the slot field is defined as a “Reserved...

  • Page 32: Table 16. Space Field Decoding

    PS6700 internal register writes. Writes will normally be completed by the CL-PS6700 device independent of the EP7312 processor activity. If a posted write times out, or fails to complete for any other reason, then the CL-PS6700 will issue an interrupt (i.e., a WR_FAIL interrupt). In the case where the CL-PS6700 write buffer is already full, the PRDY signal will be de-asserted (i.e., driven low) and the transaction will be...
  • Page 33 A GPIO signal from the EP7312 can be connected to the PSLEEP pin of the CL-PS6700 devices to allow them to be put into a power saving state before the EP7312 enters the Standby State. It is essential that the software monitor the appropriate status registers within the CL-PS6700s to ensure that there are no pend- ing posted bus transactions before the Standby State is entered.

  • Page 34: Serial Interfaces

    2.12 Serial Interfaces In addition to the two UARTs, the EP7312 offers the following serial interfaces shown in Table 17. The inputs / outputs of three of the serial interfaces (DAI, CODEC, and SSI2) are multiplexed onto a single set of external interface pins.

  • Page 35: Codec Sound Interface

    2.13 CODEC Sound Interface The CODEC interface allows direct connection of a telephony type CODEC to the EP7312. It provides all the necessary clocks and timing pulses. It also performs a parallel to serial conversion or vice versa on the data stream to or from the external CODEC device.

  • Page 36: Endianness

    Endianness. Table 19 on page 38 and Table 20 on page 38 demonstrate the behavior of the EP7312 in big and little en- dian mode, including the effect of performing non-aligned word accesses. The register definition section of this specification defines the behavior of the internal EP7312 registers in the big endian mode in more detail.

  • Page 37: Table 19. Effect Of Endianness On Read Operations

    (as seen 15:8 23:16 31:24 15:8 23: 16 31: 24 Little by the Endian Endian EP7312) Word + 0 (W) 11223344 11223344 11223344 Word + 1 (W) 11223344 44112233 44112233 Word + 2 (W) 11223344 33441122 33441122 Word + 3 (W) 11223344...

  • Page 38: Internal Uarts (Two) And Sir Encoder

    RI input, and RTS and DTR output modem control lines are not explicitly supported but can be implemented using GPIO ports in the EP7312. UART2 has only the RX and TX pins. UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). Three interrupts can be generated by UART1: RX, TX, and modem status interrupts.

  • Page 39: Digital Audio Interface

    Figure 7 on page 42. Please see Table 22 on page 42 for the MUX programming matrix. DAI 128/64 fs CODEC SSICLK, SSITXFR, SSITXDA, SSIRXDA , SSIRSFR SSI2 Figure 6. Portion of the EP7312 Block Diagram Showing Multiplexed Feature DS508UM1...

  • Page 40: Dai Operation

    2.15.1.1 DAI Operation Following reset, the DAI logic is disabled. To enable the DAI, the applications program should first clear the emergency underflow and overflow status bits, which are set following the reset, by writing a 1 to these register bits (in the DAISR register). Next, the DAI control register should be programmed with the desired mode of operation using a word write.

  • Page 41: Dai Frame Format

    Programmable Divide (AUDIV) Audio (AUDCLKSRC) Audio Sample 7-bit Data 128(fs) Frequency counter FIFO fixed at 4 (73.728MHz) (fs) Control Audio Bit Clock 128/64(fs) SCLK LRCLK(Fs) EXTCLK (11.2896) 256Fs MCLK BUZZ-PIN BUZZ Figure 7. Digital Audio Clock Generation FEATURE SYSCON2 SYSCON3 DAI64 fs DAIR(DAI) DAI –128 fs...

  • Page 42: Dai Signals

    2.15.1.3 DAI Signals MCLK oversampled clock. Used as an input to the EP7312 for generating the DAI timing. This sig- nal is also usually used as an input to a DAC/ADC as an oversampled clock. This signal is fixed at 256 times the audio sample frequency.

  • Page 43: Master / Slave Ssi2 (Synchronous Serial Interface 2)

    2.15.3 Master / Slave SSI2 (Synchronous Serial Interface 2) A second SPI / Microwire interface with full master / slave capability is provided by the EP7312 data rates in slave mode are theoretically up to 512 kbits/s, full duplex, although continuous operation at this data rate will give an interrupt rate of 2 kHz, which is too fast for many operating systems.

  • Page 44: Figure 9. Ssi2 Port Directions In Slave And Master Mode

    SSICLK cycle after they are written and the value read back from SYSCON2. The enable bits reflect the real status of the enables internally. Hence, there will be a delay before the new value programmed to the enable bits can be read back. Master EP7312 Slave EP7312 SSIRXFR...

  • Page 45: Read Back Of Residual Data

    2.15.3.1 Read Back of Residual Data All writes to the transmit FIFO must be in half-words (i.e., in units of two bytes at a time). On the receive side, it is possible that an odd number of bytes will be received. Bytes are always loaded into the receive FIFO in pairs.

  • Page 46: Continuous Data Transfer

    To disable the clock, the TX section is turned off. In Master mode, the EP7312 does not support the discontinuous clock. 2.15.3.5 Error Conditions RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register.

  • Page 47: Lcd Controller With Support For On-Chip Frame Buffer

    2.16 LCD Controller with Support for On-Chip Frame Buffer The LCD controller provides all the necessary control signals to interface directly to a single panel multi- plexed LCD. The panel size is programmable and can be any width (line length) from 32 to 1024 pixels in 16-pixel increments.

  • Page 48: Figure 11. Video Buffer Mapping

    latency is almost exactly 3.2 µs, with 13 MHz page mode cycles. With each cycle consuming ~77 ns (i.e., 1/1 MHz), the value of 3.2 µs comes from 42 cycles 77 ns/cycle = ~3.23 µs. If 16-bit wide, then the worst-case latency will double.

  • Page 49: Timer Counters

    2.18 Real Time Clock The EP7312 contains a 32-bit Real Time Clock (RTC). This can be written to and read from in the same way as the timer counters, but it is 32 bits wide. The RTC is always clocked at 1 Hz, generated from the 32.768 kHz oscillator.

  • Page 50: Characteristics Of The Real Time Clock Interface

    The voltage for the crystal must be 2.5 V + 0.2 V. Alternatively, a digital clock source can be used to drive the RTCIN pin of the EP7312. With this approach, the voltage levels of the clock source should match that of the V supply for the EP7312’s pads (i.e., the...

  • Page 51: Boundary Scan

    The boundary scan chain is selected as the default on test-logic reset and any of the system resets. The contents of the device ID-register for the EP7312 are shown in Figure 12. This is equivalent to 0x0F0F.0F0F. Note this is the ID-code for the ARM720T processor.

  • Page 52: In-Circuit Emulation

    2.23 Maximum-Configured EP7312-Based System A maximum configured system using the EP7312 is shown in Figure 13 on page 54. This system assumes all of the SDRAMs and ROMs are 16-bit wide devices. The keyboard may be connected to more GPIO bits than shown to allow greater than 64 keys, however these extra pins will not be wired into the WAKE- UP pin functionality.

  • Page 53: Figure 13. A Maximum Ep7312 Based System

    ADCCLK nCS[2] nADCCS nCS[3] DIGITIZER ADCOUT BUFFERS ADCIN LEDFLSH ADDITIONAL I/O SMPCLK LATCHES NOTE: A system can only use one of the following peripheral interfaces at any given time: SSI2, CODEC, or Figure 13. A Maximum EP7312 Based System DS508UM1...

  • Page 54: I/O Buffer Characteristics

    2.24 I/O Buffer Characteristics All I/O buffers on the EP7312 are CMOS threshold input bidirectional buffers except the oscillator and power pads. For signals that are nominally inputs, the output buffer is only enabled during pin test mode. All output buffers are three stated during system (hi-Z) test mode. All buffers have a standard CMOS threshold input stage (apart from the Schmitt-triggered inputs) and CMOS slew-rate- controlled output stages to reduce system noise.

  • Page 55: Test Modes

    3. TEST MODES The EP7312 supports a number of hardware activated test modes, these are activated by the pin combina- tions shown in Table 26. All latched signals will only alter test modes while NPOR is low, their state is latched on the rising edge of NPOR.

  • Page 56: Oscillator And Pll Test Mode

    This test mode will enable the main oscillator and will output various buffered clock and test signals de- rived from the main oscillator, PLL, and 32 kHz oscillator. All internal logic in the EP7312 will be static and isolated from the oscillators, with the exception of the 6-bit ripple counter used to generate 576 kHz and the Real Time Clock divide chain.

  • Page 57: Debug / Ice Test Mode

    This test mode asynchronously disables all output buffers on the EP7312. This has the effect of removing the EP7312 from the PCB so that other devices on the PCB can be in-circuit tested. The internal state of the EP7312 is not altered directly by this test mode.

  • Page 58: Part Ii: Pin And Register Reference

    Part II: Pin and Register Reference DS508UM1...

  • Page 59: Pin Descriptions

    4. PIN DESCRIPTIONS Table 29 describes the function of all external signals to the EP7312. Note that all output signals and all I/O pins (when acting as outputs) are three stateable. This is to enable the Hi-Z test modes to be supported.
  • Page 60 Function Signal Signal Description Name BA[0-1]/ SDRAM bank select pins A[13-14] nMOE/nSDCAS ROM expansion OP enable/ SDRAM CAS control signal nMWE/nSDWE ROM expansion write enable/ SDRAM write enable control signal nCS[0-3] Chip select; active low, SRAM-like chip selects for expansion nCS[4-5] Chip select;...
  • Page 61 Function Signal Signal Description Name External Clock EXPCLK Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input. nMEDCHG / Media changed input;...
  • Page 62 Function Signal Signal Description Name nPOR Power-on reset input. This signal is not deglitched. When active it completely resets the entire system, including all the RTC registers. Upon power-up, the signal must be held active low for a minimum of 100 µsec after V has settled.
  • Page 63 Function Signal Signal Description Name ADCCLK Serial clock output nADCCS Chip select for ADC interface ADCOUT Serial data output Interface (SSI1) ADCIN Serial data input SMPCLK Sample clock output LEDDRV Infrared LED drive output (UART1) PHDIN Photo diode input (UART1) TXD[1-2] RS232 UART1 and 2 TX outputs IrDA and...
  • Page 64 During power-on reset, PE[0] and PE[1] are inputs and are latched by BOOTSEL[1] the rising edge of nPOR to select the memory width that the EP7312 will use to read from the boot code storage device (i.e., external 8-bit- wide FLASH bank).

  • Page 65: Ssi / Codec / Dai Pin Multiplexing

    SSI / CODEC / DAI Pin Multiplexing SSI2 CODEC Direction Strength SSICLK PCMCLK SCLK SSITXFR PCMSYNC LRCK SSITXDA PCMOUT SDOUT Output SSIRXDA PCMIN SDIN Input SSIRXFR p/u* MCLK * p/u = use an ~10 k pull-up Table 30. SSI/CODEC/DAI Pin Multiplexing The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2 (See SYSCON2 System Control Register 2).

  • Page 66: Ep7312 Memory Map

    0xC000.0000 to 0xDFFF.FFFF is allocated to SDRAM. The 1.5 GByte, less 8 kbytes for internal registers, is not accessible in the EP7312. The MMU in the EP7312 should be programmed to generate an abort ex- ception for access to this area.

  • Page 67: Register Descriptions

    Internal Registers Table 33 on page 69 shows the Internal Registers of the EP7312 that are compatible with the EP7211 when the CPU is configured to a little endian memory system. Table 34 on page 72 shows the differences that occur when the CPU is configured to a big endian memory system for byte-wide access to Ports A, B, and D.

  • Page 68: Table 33. Ep7312 Internal Registers (Little Endian Mode)

    CODR CODEC data I/O register 0x8000.0480 UARTDR1 UART1 FIFO data register 0x8000.04C0 UBLCR1 UART1 bit rate and line control register 0x8000.0500 SYNCIO Synchronous serial I/O data register for master only SSI Table 33. EP7312 Internal Registers (Little Endian Mode) DS508UM1...
  • Page 69 Master / slave SSI2 data Register 0x8000.1600 SRXEOF — — Write to clear RX FIFO overflow flag 0x8000.16C0 SS2POP — — Write to pop SSI2 residual byte into RX FIFO Table 33. EP7312 Internal Registers (Little Endian Mode) (cont.) DS508UM1...
  • Page 70 0x8000.2340 SDRFPR* SDRAM Refresh Register 0x8000.2440 UNIQID* 32-bit unique ID for the EP7312 device 0x8000.2700 RANDID0* Bits 31-0 of 128-bit random ID for the EP7312 device 0x8000.2704 RANDID1* Bits 63-32 of 128-bit random ID for the EP7312 device 0x8000.2708 RANDID2*...

  • Page 71: Padr - Port A Data Register

    Table 34. EP7312 Internal Registers (Big Endian Mode) All internal registers in the EP7312 are reset (cleared to zero) by a system reset (i.e., nPOR, nURESET, or nPWRFL signals becoming active), except for the SDRAM refresh period register (DPFPR), the Real Time Clock data register (RTCDR), and the match register (RTCMR), which are only reset by nPOR be- coming active.

  • Page 72: Pddr - Port D Data Register

    (port output). Values read from this register reflect the external state of Port registers in the EP7312 are reset (cleared to zero) by a system reset (i.e., nPOR, nURESET, or nP- WRFL signals becoming active), except for the SDRAM refresh period register (SDRFPR), the Real Time Clock data register (RTCDR), and the match register (RTCMR), which are only reset by nPOR becoming active.

  • Page 73: System Control Registers

    The system control register is a 21-bit read / write register which controls all the general configuration of the EP7312, as well as modes etc. for peripheral devices. All bits in this register are cleared by a system reset. The bits in the system control register SYSCON1 are defined in Table 35.
  • Page 74 Description BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is selected (i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ (SYSCON1) bits for more details. BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin is connected directly to the BZTOG bit.
  • Page 75 Description EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously as a free running clock with the same frequency and phase as the CPU clock, assuming that the main oscillator is running. This bit should not be left set all the time for power consumption rea- sons.

  • Page 76: Syscon2- System Control Register 2

    1=16-bit DRAM. KBWEN: When the KBWEN bit is high, the EP7312 will awaken from a power saving state into the Operating State when a high signal is on one of Port A’s inputs (irrespective of the state of the interrupt mask register).
  • Page 77 Description SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will be disabled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2 interface will be in a power saving state. UART2EN: Internal UART2 enable bit.

  • Page 78: Syscon3 - System Control Register 3

    Reserved This register is an extension of SYSCON1 and SYSCON2, containing additional control for the EP7312. The bits of this third system control register are defined in Table 37. Description ADCCON: Determines whether the ADC Configuration Extension field SYNCIO[16-31] is to be used for ADC configuration data.

  • Page 79: Sysflg1 - System Status Flags Register

    PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the nPWRFL input pin, it is cleared by writing to the STFCLR location. CLDFLG: Cold start flag. This bit will be set if the EP7312 has been reset with a power on reset, it is cleared by writing to the STFCLR location.
  • Page 80 32-bit 8-bit 16-bit Reserved ID: Will always read “1” for the EP7312 device 30-31 VERID: Version ID bits. These 2 bits determine the version ID for the EP7312. Will read “01” for the initial version. Table 38. SYSFLG1 (cont.) DS508UM1...

  • Page 81: Sysflg2 - System Status Register 2

    SS2TXFF: Master / slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This will get cleared when data is removed from the FIFO or the EP7312 is reset. SS2TXUF: Master / slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans- mit when TX FIFO is empty.

  • Page 82: Interrupt Registers

    The interrupt status register is a 32-bit read only register. The interrupt status register reflects the cur- rent state of the first 16 interrupt sources within the EP7312. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Table 40.

  • Page 83: Intmr1 - Interrupt Mask Register 1

    This interrupt mask register is a 32-bit read / write register, which is used to selectively enable any of the first 16 interrupt sources within the EP7312. The four shaded interrupts all generate a fast interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address 0000.001C.

  • Page 84: Intsr2 - Interrupt Status Register 2

    SS2RX KBDINT The interrupt status register also reflects the current state of the new interrupt sources within the EP7312. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Table 41. Description KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the log- ical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register.

  • Page 85: Intsr3 - Interrupt Status Register 3

    INTMR3 — Interrupt Mask Register 3 ADDRESS: 0x8000.2280 Reserved DAIINT This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the EP7312. Please refer to INTSR3 for individual bit details. Memory Configuration Registers 6.4.1 MEMCFG1 — Memory Configuration Register 1 ADDRESS: 0x8000.0180...

  • Page 86: Memcfg2 - Memory Configuration Register 2

    BOOTBIT bits are determined by Port E bits 0 and 1 on the EP7312 during power-on reset. The state of PE[1] and PE[0] determine whether the EP7312 is going to boot from either 32-bit-wide, 16-bit-wide or 8-bit-wide ROMs.

  • Page 87: Table 43. Values Of The Bus Width Field

    Bus Width BOOTBIT1 BOOTBIT0 Expansion Transfer Port E bits 1,0 during Field Mode NPOR reset 32-bit wide bus access Low, Low 16-bit wide bus access Low, Low 8-bit wide bus access Low, Low Reserved Low, Low 8-bit wide bus access Low, High Reserved Low, High...

  • Page 88: Table 45. Values Of The Wait State Field At 36 Mhz

    Wait States Wait States Bit 3 Bit 2 Bit 1 Bit 0 Random Sequential Table 45. Values of the Wait State Field at 36 MHz Description SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a quad word boundary to take advantage of faster access times from devices that support page mode.

  • Page 89: Timer / Counter Registers

    See the “AC Electrical Specification ” section in the EP7312 Data Sheet for more details on bus timing. The memory area decoded by CS[6] is reserved for the on-chip SRAM, hence this does not require a configuration field in MEMCFG2. It is automatically set up for 32-bit-wide, no-wait-state accesses.

  • Page 90: Sdconf - Sdram Control Register

    The flash rate is determined by the LEDFLSH[0-1] bits, in the following way: LEDFLSH[0-1] Flash Period (sec) Table 47. LED Flash Rates LEDFLSH[2-5] Duty Ratio LEDFLSH[2-5] Duty Ratio (time on: time off) (time on: time off) 0000 01:15 1000 09:07 0001 02:14 1001...

  • Page 91: Sdrfpr - Sdram Refresh Period Register

    Description Control over the SDRAM clock. ‘0’=> SDRAM clock is permanently enabled except when in standby mode. ‘1’=>SDRAM clock stops when the EP7312 is put into inactive mode i.e., SDAC- TIVE = ‘0’, or when EP7312 is in standby mode.

  • Page 92: Randid1 Register

    6.11 RANDID1 Register 8000.2704 63-32 This 32-bit register is set at the factory and is used to implement the MaverickKey™ functionality and to create 128-bit unique random IDs. The unique number is read-only and cannot be modified by software. 6.12 RANDID2 Register 8000.2708 95-64 This 32-bit register is set at the factory and is used to implement the MaverickKey™...

  • Page 93: Codr - Codec Interface Data Register

    18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source. NOTE: The EP7312 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to determine which of the above fields to use. 8-11 Drive 1 pump ratio: This 4-bit field controls the “on”...

  • Page 94: Uart Registers

    6.16 UART Registers 6.16.1 UARTDR1–2, UART1–2 Data Registers ADDRESS: 0x8000.0480 and 0x8000.1480 OVERR PARERR FRMERR RX data The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the internal UARTs 1 and 2. Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled.

  • Page 95: Ubrlcr1-2 Uart1-2 Bit Rate And Line Control Registers

    6.16.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers ADDRESS: 0x8000.04C0 and 0x8000.14C0 18-17 11-0 WRDLEN FIFOEN XSTOP EVENPRT PRTEN BREAK Bit rate divisor The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers sets the bit rate and mode of operation for the internal UARTs.

  • Page 96: Lcd Registers

    Description 17-18 WRDLEN: This two bit field selects the word length according to the table below. WRDLEN Word Length 5 bits 6 bits 7 bits Table 52. UBRLCR1-2 UART1-2 (cont.) 6.17 LCD Registers 6.17.1 LCDCON — LCD Control Register ADDRESS: 0x8000.02C0 29-25 24-19 18-13...

  • Page 97: Table 53. Lcdcon

    Pixel rate (MHz) = 36.864 / (Pixel prescale + 1) When the EP7312 is operating at 13 MHz, pixel rate is given by the formula: Pixel rate (MHz) = 13 / (Pixel prescale + 1) The pixel prescale value can be expressed in terms of the LCD size by the formula: When the EP7312 is operating @ 18.432 MHz:...

  • Page 98: Pallsw - Least Significant Word - Lcd Palette Register

    6.17.2 PALLSW — Least Significant Word — LCD Palette Register ADDRESS: 0x8000.0580 31-28 27-24 23-20 19-16 15-12 11-8 Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel...

  • Page 99: Fbaddr - Lcd Frame Buffer Start Address Register

    Grayscale Value Duty Cycle % Pixels Lit % Step Change 11.1% 11.1% 8.9% 20.0% 6.7% 4/15 26.7% 6.6% 33.3% 6.7% 40.0% 5.4% 44.4% 5.6% 50.0% 0.0% 50.0% 5.6% 55.6% 5.4% 60.0% 6.7% 66.7% 6.6% 11/15 73.3% 6.7% 80.0% 8.9% 88.9% 11.1% 100% Table 54.

  • Page 100: Ssi Registers

    6.18 SSI Registers 6.18.1 SYNCIO — Synchronous Serial ADC Interface Data Register ADDRESS: 0x8000.0500 In the default mode, the bits in SYNCIO have the following meaning: 31-15 12-8 Reserved TXFRMEN SMCKEN Frame length ADC Configuration Byte In extended mode, the following applies: 12-7 Reserved TXFRMEN...

  • Page 101: Stfclr - Clear All "Start Up Reason" Flags Location

    Description 0-7 or 0-6 ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the ADC Configuration Extension field for sending to the ADC.

  • Page 102: Tc1Eoi Tc1 End Of Interrupt Location

    6.20.4 TC1EOI TC1 End of Interrupt Location ADDRESS: 0x8000.06C0 A write to this location will clear the under flow interrupt generated by TC1. 6.20.5 TC2EOI TC2 End of Interrupt Location ADDRESS: 0x8000.0700 A write to this location will clear the under flow interrupt generated by TC2. 6.20.6 RTCEOI —...

  • Page 103: State Control Registers

    Standby State. 2) If the EP7312 is attempting to get into the Standby State when there is a pending interrupt request, it will not enter into the low power mode. The instruction will get executed, but the processor will ignore the command.

  • Page 104: Dai Register Definitions

    6.23 DAI Register Definitions There are five registers within the DAI Interface, one control register, three data registers, and one status register. The control register is used to mask or unmask interrupt requests to service the DAI’s FIFOs, and to select whether an on-chip or off-chip clock is used to drive the bit rate, and to enable / disable operation.

  • Page 105: Dair - Dai Control Register

    6.23.1 DAIR — DAI Control Register ADDRESS: 0x8000.2000 31-24 15-0 Reserved Reserved RCRM RCTM LCRM LCTM Reserved DAIEN Reserved The DAI control register (DAIR) contains eight different bit fields that control various functions within the DAI interface. Description 0-15 Reserved Must be set to 0x0404 Reserved Reserved DAIEN: DAI Interface Enable...

  • Page 106: Dai Enable (Daien)

    6.23.1.1 DAI Enable (DAIEN) The DAI enable (DAIEN) bit is used to enable and disable all DAI operation. When the DAI is disabled, all of its clocks are powered down to minimize power consumption. Note that DAIEN is the only control bit within the DAI interface that is reset to a known state. It is cleared to zero to ensure the DAI timing is disabled following a reset of the device.

  • Page 107: Right Channel Receive Fifo Interrupt Mask (Rcrm)

    6.23.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) The Right Channel Receive FIFO interrupt mask (RCRM) bit is used to mask or enable the Right Channel Receive FIFO service request interrupt. When RCRM = 0, the interrupt is masked and the state of the Right Channel Receive FIFO service request (RCRS) bit within the DAI status register is ignored by the interrupt controller.

  • Page 108: Dai64Fs Control Register

    6.23.2 DAI64Fs Control Register ADDRESS: 0x8000.2600 The DAI now includes a divider network for the frequency of the clock source. The EP7312 provides for both 128 and 64 times the sample frequency (128 fs and 64 fs) to better support the various MP3 sample rates.

  • Page 109: Dai Data Registers

    6.23.3 DAI Data Registers The DAI contains three data registers: DAIDR0 addresses the top entry of the Right Channel Transmit FIFO and bottom entry of the Right Channel Receive FIFO; DAIDR1 addresses the top and bottom entry of the Left Channel Transmit and Receive FIFOs, respectively; and DAIDR2 is used to perform enable and disable the DAI FIFOs.

  • Page 110: Daidr1 - Dai Data Register 1

    6.23.3.2 DAIDR1 — DAI Data Register 1 ADDRESS: 0x8000.2080 31-16 15-0 Reserved Bottom of Left Channel Receive FIFO Read Access 31-16 15-0 Reserved Top of Left Channel Transmit FIFO Write Access When DAI Data Register 1 (DAIDR1) is read, the bottom entry of the Left Channel Receive FIFO is accessed.

  • Page 111: Daidr2 - Dai Data Register 2

    6.23.3.3 DAIDR2 — DAI Data Register 2 ADDRESS: 0x8000.20C0 31-21 20-16 14-0 Reserved FIFO Channel Select FIFOEN Reserved DAIDR2 is a 32-bit register that utilizes 21 bits and is used to enable and disable the FIFOs for the left and right channels of the DAI data stream. The left channel FIFO is enabled by writing 0x000D.8000 and disabled by writing 0x000D.0000.

  • Page 112: Daisr - Dai Status Register

    6.23.4 DAISR — DAI Status Register ADDRESS: 0x8000.2100 The DAI Status Register (DAISR) contains bits which signal FIFO overrun and underrun errors and FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller. The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty, when a FIFO operation is complete, and when the right channel or left channel portion of the CODEC is enabled (no interrupt generated).
  • Page 113 Description Right Channel Transmit FIFO Underrun 0 — Right Channel Transmit FIFO has not experienced an underrun 1 — Right Channel Transmit logic attempted to fetch data from transmit FIFO while it was empty, request interrupt RCRO: Right Channel Receive FIFO Overrun 0 —...

  • Page 114: Right Channel Transmit Fifo Service Request Flag (Rcts)

    6.23.4.1 Right Channel Transmit FIFO Service Request Flag (RCTS) The Right Channel Transmit FIFO Service Request Flag (RCTS) is a read-only bit which is set when the Right Channel Transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS is set any time the Right Channel Transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data.

  • Page 115: Left Channel Transmit Fifo Underrun Status (Lctu)

    6.23.4.7 Left Channel Transmit FIFO Underrun Status (LCTU) The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left Channel Transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the Left Channel Transmit logic continuously transmits the last valid left channel value which was transmitted before the underrun occurred.

  • Page 116: Locations / Names Of Pins

    7. LOCATIONS / NAMES OF PINS 208-Pin LQFP Pin Diagram D[25] A[25]/DRA[2] VDDOSC D[26] MOSCIN MOSCOUT A[26]/DRA[1] VSSOSC D[27] A[27]/DRA[0] WAKEUP VSSIO NPWRFL A[6] D[28] D[6] D[29] A[5] D[30] D[5] D[31] VDDIO VSSIO COL[0] A[4] COL[1] D[4] TCLK A[3] VDDIO D[3] COL[2] A[2]...

  • Page 117: 256-Pin Pbga Pin Diagram

    256-PIN PBGA PIN DIAGRAM 16 15 14 13 12 11 10 256-Ball PBGA (Bottom View) Note: For package specifications, please see EP7312 Data Sheet. Figure 15. 256-Ball Plastic Ball Grid Array Diagram DS508UM1...

  • Page 118: Appendix A: Boot Code

    8. APPENDIX A: BOOT CODE 00000000 uart_boot_base 00000000 E3A0C102 r12, #HwRegisterBase ; R12 = 0x80000000 00000004 00000004 E3A08201 r8, #InternalRamBase ; R8 = 0x10000000 00000008 E2889B02 r9, r8, #ImageSize ; R9 = 0x10000800 0000000C 0000000C ;;; The remaining code is functionally identical to the 7111 boot code 0000000C 0000000C ;;;...
  • Page 119 00000054 00000054 E3A0003E r0, #EndFlag 00000058 E5CC0480 STRB r0, [r12, #Hw_UARTDR1] ; Send reply 0000005C 0000005C 0000005C 0000005C ;;; Having loaded all the bytes, do the right thing to finish. 0000005C 0000005C 0000005C E55807FD LDRB r0, [r8, #(3-ImageSize)] 00000060 E35000FF r0, #BootImageFlagByte 00000064 00000064...
  • Page 120 NMOE/SDCAS 61 nMWE/nSDWE 61 LCD controller 48 nNEXTFIQ 62 nPOR 63 nPWRFL 62 memory and I/O expansion interface 27 nTEST 65 EP7312 boot ROM 26 nTRST 65 nURESET 63 PA 65 operating state 24 PB 65 PD 64, 65 PE 65...
  • Page 121 SMPCLK 64 Residual Byte 104 SSICLK 63 state control 104 SSIRXDA 63 STDBY Enter the Standby State Location 104 SSIRXFR 63 SYNCIO Synchronous Serial ADC Interface Data SSITXDA 63 Register 101 SSITXFR 63 SYSFLG1 System Status Flags Register 1 80 TCLK 65 SYSFLG2 System Status Register 2 82 TDI 65...

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