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Function
Signal
Name
BA[0-1]/
A[13-14]
nMOE/nSDCAS
nMWE/nSDWE
nCS[0-3]
nCS[4-5]
SDQM[0-3]
EXPRDY
Memory Inter-
face
WRITE/
nSDRAS
WORD /
HALFWORD
DS508UM1
Signal
I/O
SDRAM bank select pins
O
ROM expansion OP enable/ SDRAM CAS control signal
O
ROM expansion write enable/ SDRAM write enable control signal
O
Chip select; active low, SRAM-like chip selects for expansion
O
Chip select; active low, CS for expansion or for CL-PS6700 select
I/O
Data input/output masks
I
Expansion port ready; external expansion devices drive this low to
extend the bus cycle. This is used to insert wait states for an external
bus cycle.
O
Transfer Direction/SDRAM RAS control signal
O
To do write accesses of different sizes Word and Half-Word must be
externally decoded. The encoding of these signals is as follows:
Access
Half-Word
The core will generate an address. When doing a read, the ARM core
will select the appropriate byte channels. When doing a write, the cor-
rect bytes will have to be enabled depending on the above signals and
the least significant bits of the address bus.
The ARM architecture does not support unaligned accesses. For a
read using x 32 memory, it is assumed that you will ignore bits 1 and 0
of the address bus and perform a word read (or in power critical sys-
tems decode the relevant bits depending on the size of the access). If
an unaligned read takes place, the core will rotate the resulting data in
the register. For more information on this behavior see the LDR
instruction in the ARM7TDMI data sheet.
Table 29. External Signal Functions (cont.)
Description
Word
Size
Word
1
0
Byte
0
Half-Word
0
1
0
61
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