Maverick EP7312 User Manual page 33

A card read operation may be split into a request cycle and a data cycle, or it may be combined into a single
request/data transfer cycle. This depends on whether the data requested from the card is available in the
prefetch buffer (internal to the CL-PS6700).
The request portion of the cycle, for a card read, is similar to the request phase for a card write (described
above). If the requested data is available in the prefetch buffer, the CL-PS6700 asserts the PRDY signal
before the rising edge of the third clock and the EP7312 continues the cycle to read the data. Otherwise,
the PRDY signal is de-asserted, and the request cycle is stalled. The EP7312 may then allow the DMA
address generator to gain control of the bus, to allow LCD refreshes to continue. When the CL-PS6700 is
ready with the data, it asserts the PRDY signal. The EP7312 then arbitrates for the bus and, once the re-
quest is granted, the suspended read cycle is resumed. The EP7312 resumes the cycle by asserting the ap-
propriate chip select, and data is transferred on the next two clocks if a word read (one clock if a byte read).
There is no support within the EP7312 for detecting time-outs. The CL-PS6700 device must be pro-
grammed to force the cycle to be completed (with invalid data for a read) and then generate an interrupt if
a read or write access has timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system software can then
determine which access was not successfully completed by reading the status registers within the CL-
PS6700.
The CL-PS6700 has support for DMA data transfers. However, DMA is supported only by software emu-
lation because the DMA address generator built into the EP7312 is dedicated to the LCD controller inter-
face. If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to make a DMA request.
This can be connected to one of the EP7312's external interrupts and be used to interrupt the CPU so that
the software can service the DMA request under program control.
Each of the CL-PS6700 devices can generate an interrupt PIRQ. Since the PIRQ signal is an open drain on
the CL-PS6700 devices, two CL-PS6700 devices may be wired OR'ed to the same interrupt. The circuit
can then be connected to one of the EP7312's active low external interrupt sources. On the receipt of an
interrupt, the CPU can read the interrupt status registers on the CL-PS6700 devices to determine the cause
of the interrupt.
All transactions are synchronized to the EXPCLK output from the EP7312 in 18.432 MHz mode or the
external 13 MHz clock. The EXPCLK should be permanently enabled, by setting the EXCKEN bit in the
SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card interface and CL-
PS6700 internal write buffers need to be clocked after the EP7312 has completed its bus cycles.
A GPIO signal from the EP7312 can be connected to the PSLEEP pin of the CL-PS6700 devices to allow
them to be put into a power saving state before the EP7312 enters the Standby State. It is essential that the
software monitor the appropriate status registers within the CL-PS6700s to ensure that there are no pend-
ing posted bus transactions before the Standby State is entered. Failure to do this will result in incomplete
PC Card accesses.
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