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Manuals and User Guides for Maverick EP7312. We have
1
Maverick EP7312 manual available for free PDF download: User Manual
Maverick EP7312 User Manual (122 pages)
Brand:
Maverick
| Category:
Controller
| Size: 1.72 MB
Table of Contents
Table of Contents
2
Part I: Ep7312 User's Manual
8
1 Conventions
9
Acronyms and Abbreviations
9
Table 1. Acronyms and Abbreviations
9
Units of Measurement
10
Table 2. Unit of Measurement
10
General Conventions
11
Pin Description Conventions
11
Table 3. Pin Description Conventions
11
2 Ep7312 Functional Description
12
CPU Core
13
Figure 1. EP7312 Block Diagram
13
State Control
14
Standby State
14
Figure 2. State Diagram
14
Table 4. Peripheral Status in Different Power States
15
UART in Standby State
16
Idle State
16
Keyboard Interrupt
17
Power-Up Sequence
17
Resets
18
Clocks
19
On-Chip PLL
19
Characteristics of the PLL Interface
19
External Clock Input (13 Mhz)
20
Figure 3. CLKEN Timing Entering the Standby State
20
Figure 4. CLKEN Timing Exiting the Standby State
20
Dynamic Clock Switching When in the PLL Clocking Mode
21
Interrupt Controller
21
Table 5. Exception Priority Handling
21
Table 6. Interrupt Allocation for the First Interrupt Register
22
Table 7. Interrupt Allocation in the Second Interrupt Register
22
Table 8. Interrupt Allocation in the Third Interrupt Register
22
Interrupt Latencies in Different States
23
Operating State
23
Idle State
23
Standby State
23
Table 9. External Interrupt Sources
24
EP7312 Boot ROM
25
Table 10. Chip Select Address Ranges after Boot from On-Chip Boot ROM
25
Memory and I/O Expansion Interface
26
Table 11. Boot Options
26
SDRAM Controller
27
Table 12. SDRAM Configurations (SDRAM 32-Bit Memory Interface)
28
Table 13. SDRAM Configurations (SDRAM 16-Bit Memory Interface)
29
SDRAM Initialization
30
Table 14. SDRAM Address Pin Connections
30
CL-PS6700 PC Card Controller Interface
31
Table 15. CL-PS6700 Memory Map
31
Table 16. Space Field Decoding
32
Serial Interfaces
34
Table 17. Serial Interface Options
34
Table 18. Serial Pin Assignments
34
CODEC Sound Interface
35
Endianness
36
Figure 5. CODEC Interrupt Timing
36
Table 19. Effect of Endianness on Read Operations
37
Table 20. Effect of Endianness on Write Operations
37
Internal Uarts (Two) and SIR Encoder
38
Digital Audio Interface
39
Figure 6. Portion of the EP7312 Block Diagram Showing Multiplexed Feature
39
DAI Operation
40
Table 21. Relationship between Audio Clocks/ Clock Sources/ Sample Frequencies
40
DAI Frame Format
41
Figure 7. Digital Audio Clock Generation
41
Table 22. Matrix for Programming the MUX
41
DAI Signals
42
ADC Interface - Master Mode Only SSI1 (Synchronous Serial Interface)
42
Figure 8. EP7312 Rev B- Digital Audio Interface Timing - MSB / Left Justified Format
42
Master / Slave SSI2 (Synchronous Serial Interface 2)
43
Table 23. ADC Interface Operation Frequencies
43
Figure 9. SSI2 Port Directions in Slave and Master Mode
44
Figure 10. Residual Byte Reading
45
Read Back of Residual Data
45
Support for Asymmetric Traffic
45
Clock Polarity
46
Continuous Data Transfer
46
Discontinuous Clock
46
Error Conditions
46
LCD Controller with Support for On-Chip Frame Buffer
47
Figure 11. Video Buffer Mapping
48
Timer Counters
49
Free Running Mode
49
Prescale Mode
49
Real Time Clock
49
Characteristics of the Real Time Clock Interface
50
Dedicated LED Flasher
50
Two PWM Interfaces
50
Boundary Scan
51
Figure 12. Device ID Register
51
Table 24. Instructions Supported in JTAG Mode
51
In-Circuit Emulation
52
Introduction
52
Functionality
52
Maximum-Configured EP7312-Based System
52
Figure 13. a Maximum EP7312 Based System
53
I/O Buffer Characteristics
54
Table 25. I/O Buffer Output Characteristics
54
3 Test Modes
55
Oscillator and PLL Bypass Mode
55
Table 26. EP7312 Hardware Test Modes
55
Oscillator and PLL Test Mode
56
Table 27. Oscillator and PLL Test Mode Signals
56
Debug / ICE Test Mode
57
Hi-Z (System) Test Mode
57
Software Selectable Test Functionality
57
Table 28. Software Selectable Test Functionality
57
Part II: Pin and Register Reference
58
4 Pin Descriptions
59
External Signal Functions
59
Table 29. External Signal Functions
59
SSI / CODEC / DAI Pin Multiplexing
65
Output Bi-Directional Pins
65
Table 30. SSI/CODEC/DAI Pin Multiplexing
65
Table 31. Output Bi-Directional Pins
65
5 Ep7312 Memory Map
66
Table 32. EP7312 Memory Map in External Boot Mode
66
6 Register Descriptions
67
Internal Registers
67
Table 33. EP7312 Internal Registers (Little Endian Mode)
68
PADR - Port a Data Register
71
PBDR - Port B Data Register
71
Table 34. EP7312 Internal Registers (Big Endian Mode)
71
PADDR - Port a Data Direction Register
72
PBDDR - Port B Data Direction Register
72
PDDDR - Port D Data Direction Register
72
PDDR - Port D Data Register
72
PEDDR - Port E Data Direction Register
72
PEDR - Port E Data Register
72
System Control Registers
73
SYSCON1 - System Control Register 1
73
Table 35. SYSCON1
73
SYSCON2- System Control Register 2
76
Table 36. SYSCON2
76
SYSCON3 - System Control Register 3
78
Table 37. SYSCON3
78
SYSFLG1 - System Status Flags Register
79
Table 38. SYSFLG1
79
SYSFLG2 - System Status Register 2
81
Table 39. SYSFLG2
81
Interrupt Registers
82
INTSR1 - Interrupt Status Register 1
82
Table 40. INTSR1
82
INTMR1 - Interrupt Mask Register 1
83
INTSR2 - Interrupt Status Register 2
84
INTMR2 - Interrupt Mask Register 2
84
Table 41. INSTR2
84
INTSR3 - Interrupt Status Register 3
85
INTMR3 - Interrupt Mask Register 3
85
Memory Configuration Registers
85
MEMCFG1 - Memory Configuration Register 1
85
Table 42. INTSR3
85
MEMCFG2 - Memory Configuration Register 2
86
Table 43. Values of the Bus Width Field
87
Table 44. Values of the Wait State Field at 13 Mhz and 18 Mhz
87
Table 45. Values of the Wait State Field at 36 Mhz
88
Table 46. MEMCFG2
88
Timer / Counter Registers
89
TC1D - Timer Counter 1 Data Register
89
TC2D - Timer Counter 2 Data Register
89
RTCDR - Real Time Clock Data Register
89
RTCMR - Real Time Clock Match Register
89
LEDFLSH Register
89
SDCONF - SDRAM Control Register
90
Table 47. LED Flash Rates
90
Table 48. LED Duty Ratio
90
SDRFPR - SDRAM Refresh Period Register
91
UNIQID Register
91
RANDID0 Register
91
RANDID1 Register
92
RANDID2 Register
92
RANDID3 Register
92
PMPCON - Pump Control Register
92
CODR - CODEC Interface Data Register
93
Table 49. PMPCON
93
Table 50. Sense of PWM Control Lines
93
UART Registers
94
UARTDR1-2, UART1-2 Data Registers
94
Table 51. UARTDR1-2 UART1-2
94
UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers
95
LCD Registers
96
LCDCON - LCD Control Register
96
Table 53. LCDCON
97
PALLSW - Least Significant Word - LCD Palette Register
98
PALMSW - most Significant Word - LCD Palette Register
98
FBADDR - LCD Frame Buffer Start Address Register
99
Table 54. Grayscale Value to Color Mapping
99
SSI Registers
100
SYNCIO - Synchronous Serial ADC Interface Data Register
100
STFCLR - Clear All "Start up Reason" Flags Location
101
End of Interrupt Locations
101
BLEOI Battery Low End of Interrupt
101
MCEOI Media Changed End of Interrupt
101
TEOI Tick End of Interrupt Location
101
Table 55. SYNCIO
101
TC1EOI TC1 End of Interrupt Location
102
TC2EOI TC2 End of Interrupt Location
102
RTCEOI - RTC Match End of Interrupt
102
UMSEOI - UART1 Modem Status Changed End of Interrupt
102
COEOI - CODEC End of Interrupt Location
102
KBDEOI - Keyboard End of Interrupt Location
102
SRXEOF - End of Interrupt Location
102
State Control Registers
103
STDBY - Enter the Standby State Location
103
HALT - Enter the Idle State Location
103
SS2 Registers
103
SS2DR - Synchronous Serial Interface 2 Data Register
103
SS2POP - Synchronous Serial Interface 2 Pop Residual Byte
103
DAI Register Definitions
104
DAIR - DAI Control Register
105
Table 56. DAI Control Register
105
DAI Enable (DAIEN)
106
DAI Interrupt Generation
106
Left Channel Receive FIFO Interrupt Mask (LARM)
106
Left Channel Transmit FIFO Interrupt Mask (LCTM)
106
Right Channel Transmit FIFO Interrupt Mask (RCTM)
106
Right Channel Receive FIFO Interrupt Mask (RCRM)
107
Dai64Fs Control Register
108
Table 57. Dai64Fs Control Register
108
Table 58. Clock Source for 64 Fs and 128 Fs
108
DAI Data Registers
109
DAIDR0 - DAI Data Register 0
109
Table 59. DAI Data Register 0
109
DAIDR1 - DAI Data Register 1
110
Table 60. DAI Data Register 1
110
DAIDR2 - DAI Data Register 2
111
Table 61. DAI Data Register 2
111
DAISR - DAI Status Register
112
Table 62. DAI Control, Data and Status Register Locations
112
Left Channel Receive FIFO Service Request Flag (LCRS)
114
Left Channel Transmit FIFO Service Request Flag (LCTS)
114
Right Channel Receive FIFO Overrun Status (RCRO)
114
Right Channel Receive FIFO Service Request Flag (RCRS)
114
Right Channel Transmit FIFO Service Request Flag (RCTS)
114
Right Channel Transmit FIFO Underrun Status (RCTU)
114
FIFO Operation Completed Flag (FIFO)
115
Left Channel Receive FIFO Not Empty Flag (LCNE)
115
Left Channel Receive FIFO Overrun Status (LCRO)
115
Left Channel Transmit FIFO Not Full Flag (LCNF)
115
Left Channel Transmit FIFO Underrun Status (LCTU)
115
Right Channel Receive FIFO Not Empty Flag (RCNE)
115
Right Channel Transmit FIFO Not Full Flag (RCNF)
115
7 Locations / Names of Pins
116
208-Pin LQFP Pin Diagram
116
Figure 14. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
116
256-Pin PBGA Pin Diagram
117
Figure 15. 256-Ball Plastic Ball Grid Array Diagram
117
8 Appendix A: Boot Code
118
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