Maverick EP7312 User Manual page 6

LIST OF TABLES
Table 1. Acronyms and Abbreviations .......................................................................................... 10
Table 2. Unit of Measurement....................................................................................................... 11
Table 3. Pin Description Conventions ........................................................................................... 12
Table 4. Peripheral Status in Different Power States.................................................................... 16
Table 5. Exception Priority Handling ............................................................................................. 22
Table 6. Interrupt Allocation for the First Interrupt Register .......................................................... 23
Table 7. Interrupt Allocation in the Second Interrupt Register ...................................................... 23
Table 8. Interrupt Allocation in the Third Interrupt Register .......................................................... 23
Table 9. External Interrupt Sources .............................................................................................. 25
Table 10. Chip Select Address Ranges After Boot from On-Chip Boot ROM............................... 26
Table 11. Boot Options ................................................................................................................. 27
Table 12. SDRAM Configurations (SDRAM 32-Bit Memory Interface) ......................................... 29
Table 13. SDRAM Configurations (SDRAM 16-Bit Memory Interface) ......................................... 30
Table 14. SDRAM Address Pin Connections................................................................................ 31
Table 15. CL-PS6700 Memory Map.............................................................................................. 32
Table 16. Space Field Decoding ................................................................................................... 33
Table 17. Serial Interface Options................................................................................................. 35
Table 18. Serial Pin Assignments ................................................................................................. 35
Table 19. Effect of Endianness on Read Operations .................................................................... 38
Table 20. Effect of Endianness on Write Operations .................................................................... 38
Table 21. Relationship Between Audio Clocks/ Clock Sources/ Sample Frequencies ................. 41
Table 22. Matrix for Programming the MUX.................................................................................. 42
Table 23. ADC Interface Operation Frequencies .......................................................................... 44
Table 24. Instructions Supported in JTAG Mode .......................................................................... 52
Table 25. I/O Buffer Output Characteristics .................................................................................. 55
Table 26. EP7312 Hardware Test Modes ..................................................................................... 56
Table 27. Oscillator and PLL Test Mode Signals .......................................................................... 57
Table 28. Software Selectable Test Functionality ......................................................................... 58
Table 29. External Signal Functions ............................................................................................. 60
Table 30. SSI/CODEC/DAI Pin Multiplexing ................................................................................. 66
Table 31. Output Bi-Directional Pins ............................................................................................. 66
Table 32. EP7312 Memory Map in External Boot Mode ............................................................... 67
Table 33. EP7312 Internal Registers (Little Endian Mode) ........................................................... 69
Table 34. EP7312 Internal Registers (Big Endian Mode) ............................................................. 72
Table 35. SYSCON1 ..................................................................................................................... 74
Table 36. SYSCON2 ..................................................................................................................... 77
Table 37. SYSCON3 ..................................................................................................................... 79
Table 38. SYSFLG1 ...................................................................................................................... 80
Table 39. SYSFLG2 ...................................................................................................................... 82
Table 40. INTSR1 ......................................................................................................................... 83
Table 41. INSTR2 ......................................................................................................................... 85
Table 42. INTSR3 ......................................................................................................................... 86
Table 43. Values of the Bus Width Field ....................................................................................... 88
Table 44. Values of the Wait State Field at 13 MHz and 18 MHz ................................................. 88
Table 45. Values of the Wait State Field at 36 MHz ..................................................................... 89
Table 46. MEMCFG2 .................................................................................................................... 89
Table 47. LED Flash Rates ........................................................................................................... 91
Table 48. LED Duty Ratio ............................................................................................................. 91
Table 49. PMPCON ...................................................................................................................... 94
Table 50. Sense of PWM control lines .......................................................................................... 94
Table 51. UARTDR1-2 UART1-2 .................................................................................................. 95
Table 53. LCDCON ....................................................................................................................... 97
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