Maverick EP7312 User Manual page 69

Address Name
0x8000.0540 PALLSW
0x8000.0580 PALMSW
0x8000.05C0 STFCLR
0x8000.0600 BLEOI
0x8000.0640 MCEOI
0x8000.0680 TEOI
0x8000.06C0 TC1EOI
0x8000.0700 TC2EOI
0x8000.0740 RTCEOI
0x8000.0780 UMSEOI
0x8000.07C0 COEOI
0x8000.0800 HALT
0x8000.0840 STDBY
0x8000.0880 Reserved
–
0x8000.0FFF
0x8000.1000 FBADDR
0x8000.1100 SYSCON2
0x8000.1140 SYSFLG2
0x8000.1240 INTSR2
0x8000.1280 INTMR2
0x8000.12C0 Reserved
–
0x8000.147F
0x8000.1480 UARTDR2
0x8000.14C0 UBLCR2
0x8000.1500 SS2DR
0x8000.1600 SRXEOF
0x8000.16C0 SS2POP
70
Default RD/WR
0 RW
0 RW
— WR
— WR
— WR
— WR
— WR
— WR
— WR
— WR
— WR
— WR
— WR
0xC RW
0 RW
0 RD
0 RD
0 RW
0 RW
0 RW
0 RW
— WR
— WR
Table 33. EP7312 Internal Registers (Little Endian Mode) (cont.)
Size
32 Least significant 32-bit word of LCD palette
register
32 Most significant 32-bit word of LCD palette reg-
ister
— Write to clear all start up reason flags
— Write to clear battery low interrupt
— Write to clear media changed interrupt
— Write to clear tick and watchdog interrupt
— Write to clear TC1 interrupt
— Write to clear TC2 interrupt
— Write to clear RTC match interrupt
— Write to clear UART modem status changed
interrupt
— Write to clear CODEC sound interrupt
— Write to enter the Idle State
— Write to enter the Standby State
Write will have no effect, read is undefined
4 LCD frame buffer start address
16 System control register 2
24 System status register 2
16 Interrupt status register 2
16 Interrupt mask register 2
Write will have no effect, read is undefined
16 UART2 Data Register
32 UART2 bit rate and line control register
16 Master / slave SSI2 data Register
— Write to clear RX FIFO overflow flag
— Write to pop SSI2 residual byte into RX FIFO
Comments
DS508UM1