Maverick EP7312 User Manual page 4

6.3.3 INTSR2 - Interrupt Status Register 2 .................................................................... 85
6.3.4 INTMR2 - Interrupt Mask Register 2 ..................................................................... 85
6.3.5 INTSR3 - Interrupt Status Register 3 .................................................................... 86
6.3.6 INTMR3 - Interrupt Mask Register 3 ..................................................................... 86
6.4 Memory Configuration Registers ...................................................................................... 86
6.4.1 MEMCFG1 - Memory Configuration Register 1 .................................................... 86
6.4.2 MEMCFG2 - Memory Configuration Register 2 .................................................... 87
6.5 Timer / Counter Registers ................................................................................................. 90
6.5.1 TC1D - Timer Counter 1 Data Register ................................................................ 90
6.5.2 TC2D - Timer Counter 2 Data Register ................................................................ 90
6.5.3 RTCDR - Real Time Clock Data Register ............................................................. 90
6.5.4 RTCMR - Real Time Clock Match Register .......................................................... 90
6.6 LEDFLSH Register ........................................................................................................... 90
6.7 SDCONF - SDRAM Control Register ............................................................................. 91
6.8 SDRFPR - SDRAM Refresh Period Register ................................................................. 92
6.9 UNIQID Register ............................................................................................................... 92
6.10 RANDID0 Register .......................................................................................................... 92
6.11 RANDID1 Register .......................................................................................................... 93
6.12 RANDID2 Register .......................................................................................................... 93
6.13 RANDID3 Register .......................................................................................................... 93
6.14 PMPCON - Pump Control Register .............................................................................. 93
6.15 CODR - CODEC Interface Data Register ..................................................................... 94
6.16 UART Registers .............................................................................................................. 95
6.16.1 UARTDR1-2, UART1-2 Data Registers ............................................................... 95
6.16.2 UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers ............................... 96
6.17 LCD Registers ................................................................................................................. 97
6.17.1 LCDCON - LCD Control Register ....................................................................... 97
6.17.2 PALLSW - Least Significant Word - LCD Palette Register ............................... 99
6.17.3 PALMSW - Most Significant Word - LCD Palette Register ............................... 99
6.17.4 FBADDR - LCD Frame Buffer Start Address Register ...................................... 100
6.18 SSI Registers ................................................................................................................ 101
6.18.1 SYNCIO - Synchronous Serial ADC Interface Data Register ........................... 101
6.19 STFCLR - Clear All "Start Up Reason" Flags Location .............................................. 102
6.20 End Of Interrupt Locations ............................................................................................ 102
6.20.1 BLEOI Battery Low End of Interrupt .................................................................... 102
6.20.2 MCEOI Media Changed End of Interrupt ............................................................ 102
6.20.3 TEOI Tick End of Interrupt Location .................................................................... 102
6.20.4 TC1EOI TC1 End of Interrupt Location ............................................................... 103
6.20.5 TC2EOI TC2 End of Interrupt Location ............................................................... 103
6.20.6 RTCEOI - RTC Match End of Interrupt ............................................................. 103
6.20.7 UMSEOI - UART1 Modem Status Changed End of Interrupt ........................... 103
6.20.8 COEOI - CODEC End of Interrupt Location ...................................................... 103
6.20.9 KBDEOI - Keyboard End of Interrupt Location ................................................. 103
6.20.10 SRXEOF - End of Interrupt Location ............................................................... 103
6.21 State Control Registers ................................................................................................. 104
6.21.1 STDBY - Enter the Standby State Location ...................................................... 104
6.21.2 HALT - Enter the Idle State Location ................................................................ 104
6.22 SS2 Registers ............................................................................................................... 104
6.22.1 SS2DR - Synchronous Serial Interface 2 Data Register ................................... 104
6.22.2 SS2POP - Synchronous Serial Interface 2 Pop Residual Byte ......................... 104
6.23 DAI Register Definitions ................................................................................................ 105
6.23.1 DAIR - DAI Control Register ............................................................................. 106
6.23.1.1 DAI Enable (DAIEN) ................................................................................ 107
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