Maverick EP7312 User Manual page 5

6.23.1.2 DAI Interrupt Generation ......................................................................... 107
6.23.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ............................... 107
6.23.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................ 107
6.23.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) ............................ 107
6.23.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) ............................ 108
6.23.2 DAI64Fs Control Register .................................................................................... 109
6.23.3 DAI Data Registers .............................................................................................. 110
6.23.3.1 DAIDR0 - DAI Data Register 0 .............................................................. 110
6.23.3.2 DAIDR1 - DAI Data Register 1 .............................................................. 111
6.23.3.3 DAIDR2 - DAI Data Register 2 .............................................................. 112
6.23.4 DAISR - DAI Status Register ............................................................................. 113
6.23.4.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................. 115
6.23.4.2 Right Channel Receive FIFO Service Request Flag (RCRS) .................. 115
6.23.4.3 Left Channel Transmit FIFO Service Request Flag (LCTS) .................... 115
6.23.4.4 Left Channel Receive FIFO Service Request Flag (LCRS) ..................... 115
6.23.4.5 Right Channel Transmit FIFO Underrun Status (RCTU) ......................... 115
6.23.4.6 Right Channel Receive FIFO Overrun Status (RCRO) ........................... 115
6.23.4.7 Left Channel Transmit FIFO Underrun Status (LCTU) ............................ 116
6.23.4.8 Left Channel Receive FIFO Overrun Status (LCRO) .............................. 116
6.23.4.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ............................... 116
6.23.4.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ......................... 116
6.23.4.11 Left Channel Transmit FIFO Not Full Flag (LCNF) ................................ 116
6.23.4.12 Left Channel Receive FIFO Not Empty Flag (LCNE) ............................ 116
6.23.4.13 FIFO Operation Completed Flag (FIFO) ................................................ 116
7. LOCATIONS / NAMES OF PINS .......................................................................................... 117
7.1 208-Pin LQFP Pin Diagram ............................................................................................. 117
7.2 256-Pin PBGA Pin Diagram ............................................................................................ 118
8. APPENDIX A: BOOT CODE ................................................................................................ 119
LIST OF FIGURES
Figure 1. EP7312 Block Diagram .................................................................................................. 14
Figure 2. State Diagram ................................................................................................................ 15
Figure 3. CLKEN Timing Entering the Standby State ................................................................... 21
Figure 4. CLKEN Timing Exiting the Standby State ...................................................................... 21
Figure 5. CODEC Interrupt Timing ................................................................................................ 37
Figure 6. Portion of the EP7312 Block Diagram Showing Multiplexed Feature ............................ 40
Figure 7. Digital Audio Clock Generation ...................................................................................... 42
Figure 8. EP7312 Rev B- Digital Audio Interface Timing - MSB / Left Justified format ................ 43
Figure 9. SSI2 Port Directions in Slave and Master Mode ............................................................ 45
Figure 10. Residual Byte Reading................................................................................................. 46
Figure 11. Video Buffer Mapping................................................................................................... 49
Figure 12. Device ID Register ....................................................................................................... 52
Figure 13. A Maximum EP7312 Based System ............................................................................ 54
Figure 14. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram......................................... 117
Figure 15. 256-Ball Plastic Ball Grid Array Diagram ................................................................... 118
Figure 15. 256-Ball Plastic Ball Grid Array Diagram ................................................................... 118
6 DS508UM1