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Function
Signal
Name
nPOR
State Control
RUN/CLKEN
WAKEUP
nURESET
SSICLK
SSITXFR
DAI, CODEC
or
SSITXDA
SSI2
Interface
SSIRXDA
(See Table 30
on page 66 for
pin assign-
ment and
direction fol-
lowing multi-
plexing)
SSIRXFR
DS508UM1
Signal
I
Power-on reset input. This signal is not deglitched. When active it
completely resets the entire system, including all the RTC registers.
Upon power-up, the signal must be held active low for a minimum of
100 µsec after V
to be held low for at least one clock cycle of the selected clock speed
(i.e., when running at 13 MHz, the pulse width of nPOR needs to be >
77 nsec).
Note that nURESET, RUN/CLKEN, TEST[0], TEST[1], PE[0], PE[1],
PE[2], DRIVE[0], DRIVE[1], DD[0], DD[1], DD[2], and DD[3] are all
latched on the rising edge of nPOR.
O
This pin is programmed to either output the RUN signal or the CLKEN
signal. The CLKENSL bit is used to configure this pin. When RUN is
selected, the pin will be high when the system is active or idle, low
while in the Standby State. When CLKEN is selected, the pin will only
be driven low when in the Standby State (For RUN, see Table 31 on
page 66).
1
I
Wake up is a deglitched input signal. It must also be held high for at
least 125 µsec to guarantee its detection. Once detected it forces the
system into the Operating State from the Standby State. It is only
active when the system is in the Standby State. This pin is ignored
when the system is in the Idle or Operating State. It is used to wakeup
the system after first power-up, or after software has forced the system
into the Standby State. WAKEUP will be ignored for up to two seconds
after nPOR goes HIGH. Therefore, the external WAKEUP logic must
be designed to allow it to rise and stay HIGH for at least 125 usec, two
seconds after nPOR goes HIGH.
1
I
User reset input; active low deglitched input from user reset button.
This pin is also latched upon the rising edge of nPOR and read along
with the input pins nTEST[0-1] to force the device into special test
modes. nURESET does not reset the RTC.
I/O
DAI/CODEC/SSI2 clock signal
I/O
DAI/CODEC/SSI2 serial data output frame/synchronization pulse out-
put
O
DAI/CODEC/SSI2 serial data output
I
DAI/CODEC/SSI2 serial data input
I/O
SSI2 serial data input frame/synchronization pulseDAI external clock
input
Table 29. External Signal Functions (cont.)
Description
has settled. During normal operation, nPOR needs
DD
63
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