Maverick EP7312 User Manual page 113

Bit
4 Right Channel Transmit FIFO Underrun
0 — Right Channel Transmit FIFO has not experienced an underrun
1 — Right Channel Transmit logic attempted to fetch data from transmit FIFO while it was
empty, request interrupt
5 RCRO: Right Channel Receive FIFO Overrun
0 — Right Channel Receive FIFO has not experienced an overrun
1 — Right Channel Receive logic attempted to place data into receive FIFO while it was full,
request interrupt
6 LCTU: Left Channel Transmit FIFO Underrun
0 — Left Channel Transmit FIFO has not experienced an underrun
1 — Left Channel Transmit logic attempted to fetch data from transmit FIFO while it was empty,
request interrupt
7 LCRO: Left Channel Receive FIFO Overrun
0 — Left Channel Receive FIFO has not experienced an overrun
1 — Left Channel Receive logic attempted to place data into receive FIFO while it was full,
request interrupt
8 RCNF: Right Channel Transmit FIFO Not Full (read-only)
0 — Right Channel Transmit FIFO is full
1 — Right Channel Transmit FIFO is not full
9 RCNE: Right Channel Receive FIFO Not Empty (read-only)
0 — Right Channel Receive FIFO is empty
1 — Right Channel Receive FIFO is not empty
10 LCNF: LCNETelecom Transmit FIFO Not Full (read-only)
0 — Left Channel Transmit FIFO is full
1 — Left Channel Transmit FIFO is not full
11 LCNE: Left Channel Receive FIFO Not Empty (read-only)
0 — Left Channel Receive FIFO is empty
1 — Left Channel Receive FIFO is not empty
12 FIFO: FIFO Operation Completed (read-only)0 — A FIFO Operation has not completed since
the last time this bit was cleared1 — THe FIFO Operation was completed
13 Reserved
14 Reserved
15 Reserved
16-31 Reserved
114
DAI
Control, Data and Status Register Locations (cont.)
Table 62.
Description
DS508UM1