GE T35 Instruction Manual page 423

CHAPTER 5: SETTINGS
The UR uses a novel definition of the restraining signal to cope with the above stability problems while providing fast and
sensitive protection. Even with the improved definition of the restraining signal, the breaker-and-a-half application of the
restricted ground fault must be approached with care, and is not recommended unless the settings are carefully selected
to avoid maloperation due to CT saturation.
The differential current is produced as an unbalance current between the ground current of the neutral CT (IG) and the
neutral current derived from the phase CTs (IN = IA + IB + IC):
The relay automatically matches the CT ratios between the phase and ground CTs by re-scaling the ground CT to the
phase CT level. The restraining signal ensures stability of protection during CT saturation conditions and is produced as a
maximum value between three components related to zero, negative, and positive-sequence currents of the three phase
CTs as follows:
The zero-sequence component of the restraining signal (IR0) is meant to provide maximum restraint during external
ground faults, and therefore is calculated as a vectorial difference of the ground and neutral currents:
The equation above brings an advantage of generating the restraining signal of twice the external ground fault current,
while reducing the restraint below the internal ground fault current. The negative-sequence component of the restraining
signal (IR2) is meant to provide maximum restraint during external phase-to-phase faults and is calculated as follows:
Following complete de-energization of the windings (all three phase currents below 5% of nominal for at least five cycles),
the relay uses a multiplier of 1 in preparation for the next energization. The multiplier of 3 is used during normal operation;
that is, two cycles after the winding has been energized. The lower multiplier is used to ensure better sensitivity when
energizing a faulty winding.
The positive-sequence component of the restraining signal (IR1) is meant to provide restraint during symmetrical
conditions, either symmetrical faults or load, and is calculated according to the following algorithm:
1 If |I_1| > 2 pu of phase CT, then
2 If |I_1| > |I_0|, then IR1 = 3 x (|I_1| - |I_0|)
3 else IR1 = 0
4 else IR1 = |I_1|/8
Under load-level currents (below 150% of nominal), the positive-sequence restraint is set to 1/8th of the positive-sequence
current (line 4). This is to ensure maximum sensitivity during low-current faults under full load conditions. Under fault-level
currents (above 150% of nominal), the positive-sequence restraint is removed if the zero-sequence component is greater
than the positive-sequence (line 3), or set at the net difference of the two (line 2).
The raw restraining signal (Irest) is further post-filtered for better performance during external faults with heavy CT
saturation and for better switch-off transient control:
where
k represents a present sample
k – 1 represents the previous sample
α is a factory constant (α < 1)
The equation above introduces a decaying memory to the restraining signal. Should the raw restraining signal (Irest)
disappear or drop significantly, such as when an external fault gets cleared or a CT saturates heavily, the actual
restraining signal (Igr(k)) does not reduce instantly but keeps decaying decreasing its value by 50% each 15.5 power
system cycles.
Having the differential and restraining signals developed, the element applies a single slope differential characteristic with
a minimum pickup as shown in the following logic diagram.
T35 TRANSFORMER PROTECTION SYSTEM – INSTRUCTION MANUAL
Igd = |IG + IN| = |IG + IA + IB + IC|
Irest = max(IR0, IR1, IR2)
IR0 = |IG - IN| = |IG - (IA +IB +IC)|
IR2 = |I_2| or IR2 = 3 x |I_2|
α
Igr(k) = max(Irest(k), x Igr(k - 1))
GROUPED ELEMENTS
Eq. 5-40
Eq. 5-41
Eq. 5-42
Eq. 5-43
5
Eq. 5-44
5-221