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Figure 4.4: Advanced Chipset features screen
4.5.1 DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is By SPD.
4.5.2 CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The system board designer
should set the values in this field, depending on the DRAM installed. Do not change the
values in this field unless you change specifications of the installed DRAM or the installed
CPU.
4.5.3 Active to Precharge Delay
The default setting for the Active to Precharge Delay is 7.
4.5.4 DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS
(Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read from
or refreshed. Reducing the delay improves the performance of the SDRAM.
4.5.5 DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge before
the SDRAM refreshes. The default setting for the Active to Precharge Delay is 3.
4.5.6 DRAM Data Integrity Mode
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