I/O Ports - Microchip Technology PIC16F87XA Datasheet

4.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
4.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open-drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog V input for both the A/D converters
REF
and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits
in the ADCON1 and/or CMCON registers.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
The comparators are in the off (digital)
state.
The TRISA register controls the direction of the port
pins even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
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PIC16F87XA
EXAMPLE 4-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as '0'.
FIGURE 4-1: BLOCK DIAGRAM OF
RA3:RA0 PINS
Data Latch
Data
Bus
D Q
WR
PORTA
CK Q
TRIS Latch
D Q
WR
TRISA
CK Q
RD
TRISA
RD PORTA
To A/D Converter or Comparator
Note 1: I/O pins have protection diodes to V
010-62245566
V
DD
(1)
P
I/O pin
N
V
SS
Analog
Input
Mode
TTL
Input
Buffer
Q D
EN
and V .
DD SS
DS39582B-page 41
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