Microchip Technology PIC16F87XA Datasheet page 100

PIC16F87XA
9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 9-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
BRG
Value
BRG
Reload
DS39582B-page 98
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DX
SCL deasserted but slave holds
SCL low (clock arbitration)
03h 02h 01h
SCL is sampled high, reload takes
place and BRG starts its count
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 9-17).
DX-1
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
00h (hold off) 03h 02h
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