Microchip Technology PIC16F87XA Datasheet page 162

PIC16F87XA
TABLE 15-2: PIC16F87XA INSTRUCTION SET
Mnemonic,
Operands
ADDWF f, d Add W and f
ANDWF f, d AND W with f
CLRF f Clear f
CLRW - Clear W
COMF f, d Complement f
DECF f, d Decrement f
DECFSZ f, d Decrement f, Skip if 0
INCF
f, d Increment f
INCFSZ f, d Increment f, Skip if 0
IORWF f, d
Inclusive OR W with f
MOVF f, d Move f
MOVWF f Move W to f
NOP - No Operation
RLF f, d Rotate Left f through Carry
RRF f, d Rotate Right f through Carry
SUBWF f, d Subtract W from f
SWAPF f, d
Swap nibbles in f
XORWF f, d Exclusive OR W with f
BCF f, b Bit Clear f
BSF f, b Bit Set f
BTFSC f, b Bit Test f, Skip if Clear
BTFSS f, b Bit Test f, Skip if Set
ADDLW k Add Literal and W
ANDLW k AND Literal with W
CALL k Call Subroutine
CLRWDT - Clear Watchdog Timer
GOTO k Go to Address
IORLW k Inclusive OR Literal with W
MOVLW k Move Literal to W
RETFIE - Return from Interrupt
RETLW k Return with Literal in W
RETURN - Return from Subroutine
SLEEP - Go into Standby mode
SUBLW k Subtract W from Literal
XORLW
k Exclusive OR Literal with W
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro
Family Reference Manual (DS33023).
DS39582B-page 160
http://www.xinpian.net
Description
BYTE-ORIENTED FILE REGISTER OPERATIONS
BIT-ORIENTED FILE REGISTER OPERATIONS
LITERAL AND CONTROL OPERATIONS
提供单片机解密、IC解密、芯片解密业务
14-Bit Opcode
Cycles
MSb
1
00 0111 dfff
1
00 0101 dfff
1
00 0001 lfff
1
00 0001 0xxx
1
00 1001 dfff
1
00 0011 dfff
1(2)
00 1011 dfff
1
00 1010 dfff
1(2)
00 1111
dfff
1
00 0100 dfff
1
00 1000 dfff
1
00 0000 lfff
1
00 0000 0xx0
1
00 1101 dfff
1
00 1100 dfff
1
00 0010 dfff
1
00 1110 dfff
1
00 0110 dfff
1
01 00bb bfff
1
01 01bb bfff
1 (2)
01 10bb
bfff
1 (2)
01 11bb bfff
1
11 111x kkkk
1
11 1001 kkkk
2
10 0kkk kkkk
1
00 0000 0110
2
10 1kkk
kkkk
1
11 1000 kkkk
1
11 00xx kkkk
2
00 0000 0000
2
11 01xx kkkk
2
00 0000 0000
1
00 0000 0110
1
11 110x kkkk
1
11 1010 kkkk
 2003 Microchip Technology Inc.
010-62245566
Status
Notes
Affected
LSb
C,DC,Z 1,2
ffff
Z 1,2
ffff
Z 2
ffff
Z
xxxx
Z 1,2
ffff
Z 1,2
ffff
1,2,3
ffff
Z 1,2
ffff
1,2,3
ffff
Z 1,2
ffff
Z 1,2
ffff
ffff
0000
C 1,2
ffff
C 1,2
ffff
C,DC,Z 1,2
ffff
1,2
ffff
Z 1,2
ffff
1,2
ffff
1,2
ffff
3
ffff
3
ffff
C,DC,Z
kkkk
Z
kkkk
kkkk
TO ,PD
0100
kkkk
Z
kkkk
kkkk
1001
kkkk
1000
TO,PD
0011
C,DC,Z
kkkk
Z
kkkk
®
Mid-Range MCU
13810019655