Microchip Technology PIC16(L)F1773 Manual

Microchip Technology PIC16(L)F1773 Manual

28/40/44-pin, 8-bit flash microcontroller

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28/40/44-Pin, 8-Bit Flash Microcontroller
Description
PIC16(L)F1777/8/9 microcontrollers feature a high level of integration of intelligent analog and digital peripherals for a
wide range of applications, such as lighting, power supplies, battery charging, motor control and other general purpose
applications. These devices deliver multiple op amps, 5-/10-bit DACs, high-speed comparators, 10-bit ADC, 10-/16-bit
PWMs, programmable ramp generator (PRG) and other peripherals that can be connected internally to create closed-
loop systems without using pins or the printed circuit board (PCB) area. The 10-/16-bit PWMs, digital signal modulators
and tri-state output op amp can be used together to create a LED dimming engine for lighting applications. The
peripheral pin select (PPS) functionality provides flexibility, eases PCB layout and peripheral utilization by allowing
digital peripheral pin mapping to an I/O.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Five 8-Bit Timers
• Three 16-Bit Timers
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extended Watchdog Timer (EWDT):
- Low-power 31 kHz WDT
- Software selectable prescaler
- Software selectable enable
Memory
• Up to 28 Kbytes Program Flash Memory (PFM)
• Up to 2 Kbytes Data RAM
• Direct, Indirect and Relative Addressing modes
• High-Endurance Flash (HEF):
- 128B of nonvolatile data storage
- 100K Erase/Write cycles
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1777/8/9)
- 2.3V to 5.5V (PIC16F1777/8/9)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
 2015-2016 Microchip Technology Inc.
PIC16(L)F1777/8/9
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
- 8 uA @ 31 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Intelligent Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 28 external channels
- Conversion available during Sleep
• Four Operational Amplifiers (OPA):
- Selectable internal and external channels
- Tri-state output
- Part of LED dimming engine
- Selectable internal and external channels
• Eight High-Speed Comparators (HS Comp):
- Up to nine external inverting inputs
- Up to 12 external non-inverting inputs
- Fixed Voltage Reference at inverting and
non-inverting input(s)
- Comparator outputs externally accessible
• Digital-to-Analog Converters (DAC):
- Four 10-bit resolution DACs
- 10-bit resolution, rail-to-rail
- Conversion during Sleep
- Internal connections to ADCs and HS
Comparators
• Voltage Reference:
- Fixed Voltage Reference (FVR)
- 1.024V, 2.048V and 4.096V output levels
• Zero-Cross Detector (ZCD):
- Detect high-voltage AC signal
• Four Programmable Ramp Generators (PRG):
- Slope compensation
- Ramp generation
• High-Current Drive I/Os:
- Up to 100 mA sink or source @ 5V
DS40001819B-page 1

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Summary of Contents for Microchip Technology PIC16(L)F1773

  • Page 1 - Extended: -40°C to 125°C - Detect high-voltage AC signal • Four Programmable Ramp Generators (PRG): - Slope compensation - Ramp generation • High-Current Drive I/Os: - Up to 100 mA sink or source @ 5V  2015-2016 Microchip Technology Inc. DS40001819B-page 1...
  • Page 2 One pin is input-only. Note 1: I – Debugging integrated on chip. Data Sheet Index: DS40001810 PIC16(L)F1773/6 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers DS40001819 PIC16(L)F1777/8/9 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers For other small form-factor package availability and marking information, please visit Note: or contact your local sales office.
  • Page 3 PIC16(L)F1777/8/9 TABLE 2: PACKAGES Packages SPDIP PDIP SOIC SSOP UQFN TQFP     PIC16(L)F1778     PIC16(L)F1777/9 Pin details are subject to change. Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 3...
  • Page 4 28-PIN SPDIP, SOIC, SSOP RB7/ICSPDAT /MCLR/RE3 RB6/ICSPCLK Table 3 for location of all peripheral functions. Note: FIGURE 2: 28-PIN UQFN (6x6x0.5 mm) 27 26 PIC16(L)F1778 9 10 Table 3 for location of all peripheral functions. Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 4...
  • Page 5 Note: FIGURE 4: 40-PIN UQFN (5x5x0.5 mm) 40 39 PIC16(L)F1777/9 12 13 14 15 16 17 18 19 20 Table 4 for location of all peripheral functions. Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 5...
  • Page 6 12 13 14 15 16 17 18 19 20 21 22 Table 4 for location of all peripheral functions. Note: FIGURE 6: 44-PIN QFN (8X8 mm) PIC16F1777/9 Table 4 for location of all peripheral functions. Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 6...
  • Page 7 PIN ALLOCATION TABLES TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778) — — — C1IN0- — — — — — — CLCIN0 — — — — — C2IN0- C3IN0- C4IN0- C5IN0- C6IN0- — — OPA1OUT C1IN1- — PRG1IN0 — — — — CLCIN1 —...
  • Page 8 TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED) AN11 — — — C3IN1+ — — — — — — MD3CH — — — — AN13 DAC5REF1- — — C4IN2- — — — CCP7 — — MD3MOD — — — — DAC7REF1- —...
  • Page 9 TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1778) (CONTINUED) — — — — — — C1OUT — — — PWM3 CCP1 COG1A CLC1OUT MD1OUT — — — — C2OUT PWM4 CCP2 COG1B CLC2OUT MD2OUT C3OUT PWM5 CCP7 COG1C CLC3OUT MD3OUT C4OUT PWM6 COG1D CLC4OUT C5OUT...
  • Page 10 TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) — — — C1IN0- — — — — — — CLCIN0 — — — — — C2IN0- C3IN0- C4IN0- C5IN0- C6IN0- C7IN0- C8IN0- — — OPA1OUT C1IN1- — PRG1IN0 — — — — CLCIN1 —...
  • Page 11 TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED) AN13 DAC5REF1- — — C4IN2- — — — — CCP7 — — MD3MOD — — — — DAC7REF1- — DAC5REF1+ — — C4IN1+ — — — — — — CLCIN2 — — — —...
  • Page 12 TABLE 4: 40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED) DAC6REF1+ — — — — — — — — — — — — — — — — DAC8REF1+ DAC6REF1- DAC6OUT1 — — — — — — — — — — — — — —...
  • Page 13: Table Of Contents

    35.0 Instruction Set Summary ................................526 36.0 Electrical Specifications................................540 37.0 DC and AC Characteristics Graphs and Charts ........................575 38.0 Development Support................................599 39.0 Packaging Information................................603 Appendix A: Data Sheet Revision History ............................625  2015-2016 Microchip Technology Inc. DS40001819B-page 13...
  • Page 14 When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at to receive the most current information on all of our products. www.microchip.com  2015-2016 Microchip Technology Inc. DS40001819B-page 14...
  • Page 15: Device Overview

    ● ● CCP7 ● ● 16-bit Timers CCP8 ● Timer1 ● ● Comparators Timer3 ● ● ● ● Timer5 ● ● ● ● ● ● ● ● ● ● ● ● ● ●  2015-2016 Microchip Technology Inc. DS40001819B-page 15...
  • Page 16 G1EN = 1 instruction. In assembly, exception category will not have this table. These this bit can be set with the BSF COG1CON0,G1EN peripherals include, but are not limited to, the following: instruction. • EUSART • MSSP  2015-2016 Microchip Technology Inc. DS40001819B-page 16...
  • Page 17 Figure 1-1 MCLR PORTE DSMs PRGs Timers Timers DACs Op Amps PWMs MSSP Comparators 8-bit 16-bit 5-bit Temp. DACs CLCs CCPs EUSART Indicator 10-Bit 10-bit See applicable chapters for more information on peripherals. Note  2015-2016 Microchip Technology Inc. DS40001819B-page 17...
  • Page 18 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 18...
  • Page 19 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 19...
  • Page 20 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 20...
  • Page 21 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 21...
  • Page 22 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 22...
  • Page 23 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 23...
  • Page 24 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 24...
  • Page 25 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 25...
  • Page 26 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 26...
  • Page 27 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 27...
  • Page 28 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 28...
  • Page 29 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 29...
  • Page 30 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 30...
  • Page 31 All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2016 Microchip Technology Inc. DS40001819B-page 31...
  • Page 32 PPS selection feature, it is not necessary to do so. Table 1-4 shows all the possible inter-peripheral signal connections. Please refer to cor- responding peripheral section to obtain the multiplexer selection codes for the desired connection.  2015-2016 Microchip Technology Inc. DS40001819B-page 32...
  • Page 33 ● HFINTOSC ● ● ● ● ● ● LFINTOSC ● ● ● MFINTOSC ● IOCIF ● ● ● PPS Input pin ● ● ● ● ● ● ● ● ● ● ● ●  2015-2016 Microchip Technology Inc. DS40001819B-page 33...
  • Page 34: Enhanced Mid-Range Cpu

    Decode and Decode & Decode & Control Control Control Power-on OSC1/CLKIN Reset Timing Timing Timing Watchdog W reg OSC2/CLKOUT Generation Generation Generation Timer Brown-out Reset Internal Internal Internal Oscillator Oscillator Oscillator Block Block Block  2015-2016 Microchip Technology Inc. DS40001819B-page 34...
  • Page 35 Section 3.7 “Indirect Addressing” Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See for more Section 35.0 “Instruction Set Summary” details.  2015-2016 Microchip Technology Inc. DS40001819B-page 35...
  • Page 36: Memory Organization

    Last Program Memory High-Endurance Flash Device (Words) Address Memory Address Range PIC16(L)F1777 8,192 1FFFh 1F80h-1FFFh PIC16(L)F1778/9 16,384 3FFFh 3F80h-3FFFh High-endurance Flash applies to the low byte of each address in the range. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 36...
  • Page 37 1800h Page 3 Page 3 1FFFh 1FFFh 2000h 2000h Rollover to Page 0 Page 4 Page 7 3FFFh 4000h Rollover to Page 0 Rollover to Page 3 Rollover to Page 7 7FFFh 7FFFh  2015-2016 Microchip Technology Inc. DS40001819B-page 37...
  • Page 38 FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit<7> if a label points to a location in program memory.  2015-2016 Microchip Technology Inc. DS40001819B-page 38...
  • Page 39 STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON  2015-2016 Microchip Technology Inc. DS40001819B-page 39...
  • Page 40 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the Note 1: second operand.  2015-2016 Microchip Technology Inc. DS40001819B-page 40...
  • Page 41 There are 16 bytes of common RAM accessible from all banks. Common RAM (16 bytes) 3.4.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Tables through 3-16.  2015-2016 Microchip Technology Inc. DS40001819B-page 41...
  • Page 42 TABLE 3-3: PIC16(L)F1778 MEMORY MAP (BANKS 0-7) BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 000h 080h 100h 180h 200h 280h 300h 380h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 43 TABLE 3-4: PIC16(L)F1777/9 MEMORY MAP (BANKS 0-7) BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 000h 080h 100h 180h 200h 280h 300h 380h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 44 TABLE 3-5: PIC16(L)F1778 MEMORY MAP, BANK 8-15 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 400h 480h 500h 580h 600h 680h 700h 780h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 45 TABLE 3-6: PIC16(L)F1777 MEMORY MAP, BANK 8-15 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 400h 480h 500h 580h 600h 680h 700h 780h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 46 TABLE 3-7: PIC16(L)F1779 MEMORY MAP, BANK 8-15 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 400h 480h 500h 580h 600h 680h 700h 780h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 47 TABLE 3-8: PIC16(L)F1778 MEMORY MAP, BANK 16-23 BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h 880h 900h 980h A00h A80h B00h B80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 48 TABLE 3-9: PIC16(L)F1777 MEMORY MAP, BANK 16-23 BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h 880h 900h 980h A00h A80h B00h B80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 49 TABLE 3-10: PIC16(L)F1779 MEMORY MAP, BANK 16-23 BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h 880h 900h 980h A00h A80h B00h B80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 50 TABLE 3-11: PIC16(L)F1778 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 51 TABLE 3-12: PIC16(L)F1777 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 52 TABLE 3-13: PIC16(L)F1779 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 53 F3Eh — DBFh PWM11LDCON E3Fh — EBFh — F3Fh — DC0h E40h EC0h F40h PWM11OFCON — DC1h — — — DEFh E6Fh EEFh F6Fh Legend: = Unimplemented data memory locations, read as ‘0’,  2015-2016 Microchip Technology Inc. DS40001819B-page 53...
  • Page 54 PWM12LDCON E3Fh EBFh F3Fh DCFh PWM12LDCON E3Fh EBFh F3Fh DD0h PWM12OFCON E6Fh EEFh F6Fh DD1h - E6Fh EEFh F6Fh — DEFh E6Fh EEFh F6Fh Legend: = Unimplemented data memory locations, read as ‘0’,  2015-2016 Microchip Technology Inc. DS40001819B-page 54...
  • Page 55 STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh — FECh FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’,  2015-2016 Microchip Technology Inc. DS40001819B-page 55...
  • Page 56 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 56...
  • Page 57 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0 00Ch PORTA xxxx xxxx uuuu uuuu 00Dh PORTB xxxx xxxx uuuu uuuu...
  • Page 58 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 1 08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3...
  • Page 59 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 2 10Ch LATA LATA7 LATA6 LATA5 LATA4 LATA3...
  • Page 60 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 3 18Ch ANSELA — — ANSA5 ANSA4 ANSA3...
  • Page 61 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 4 20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3...
  • Page 62 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 5 28Ch ODCONA ODA7 ODA6 ODA5 ODA4 ODA3...
  • Page 63 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 6 30Ch SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3...
  • Page 64 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 7 38Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3...
  • Page 65 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 8 40Ch — — Unimplemented —...
  • Page 66 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 9 48Ch — Unimplemented — —...
  • Page 67 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 10 50Ch — — Unimplemented —...
  • Page 68 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 11 58Ch — Unimplemented — —...
  • Page 69 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 12 60Ch — Unimplemented — —...
  • Page 70 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 13 68Ch — Unimplemented — —...
  • Page 71 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 14 70Ch — Unimplemented — —...
  • Page 72 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 15 78Ch — — Unimplemented —...
  • Page 73 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 16 80Ch — Unimplemented — —...
  • Page 74 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 17 88Ch — Unimplemented — —...
  • Page 75 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 18 90Ch CM4CON0 — Reserved SYNC 00-0 0100 00-0 0100...
  • Page 76 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 26 D0Ch — — Unimplemented —...
  • Page 77 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 27 D8Ch — Unimplemented — —...
  • Page 78 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 27 (Continued) DABh PWM6CON — MODE<1:0>...
  • Page 79 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 27 (Continued) DC1h PWM12PHL PH<7:0> xxxx xxxx uuuu uuuu DC2h PWM12PHH...
  • Page 80 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 28 E0Ch — Unimplemented — —...
  • Page 81 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 28 (Continued) E27h MD3CLPPS — —...
  • Page 82 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 29 E8Ch — — Unimplemented —...
  • Page 83 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 29 (Cont.) EA8h RD0PPS — —...
  • Page 84 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 30 F0Ch — — Unimplemented —...
  • Page 85 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 30 (Continued) F2Bh CLC3GLS1 G2D4T G2D4N G2D3T G2D3N...
  • Page 86 TABLE 3-18: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 31 F8Ch — Unimplemented — —...
  • Page 87 GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).  2015-2016 Microchip Technology Inc. DS40001819B-page 87...
  • Page 88 Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL register will 0x05 return the contents of stack address 0x04 0x0F. 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2015-2016 Microchip Technology Inc. DS40001819B-page 88...
  • Page 89 Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2015-2016 Microchip Technology Inc. DS40001819B-page 89...
  • Page 90 The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2015-2016 Microchip Technology Inc. DS40001819B-page 90...
  • Page 91 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Address Range Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.  2015-2016 Microchip Technology Inc. DS40001819B-page 91...
  • Page 92 Direct Addressing Indirect Addressing From Opcode FSRxH FSRxL 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2015-2016 Microchip Technology Inc. DS40001819B-page 92...
  • Page 93 0 0 1 Location Select 0x8000 Location Select 0x0000 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory Bank 2 (low 8 bits) 0x16F 0xF20 Bank 30 0x7FFF 0xFFFF 0xF6F 0x29AF  2015-2016 Microchip Technology Inc. DS40001819B-page 93...
  • Page 94: Device Configuration

    8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Words is Note: managed automatically device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2015-2016 Microchip Technology Inc. DS40001819B-page 94...
  • Page 95 11 = ON WDT enabled 10 = NSLEEP WDT enabled while running and disabled in Sleep 01 = SWDTEN WDT controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT disabled  2015-2016 Microchip Technology Inc. DS40001819B-page 95...
  • Page 96 The entire Flash program memory will be erased when the code protection is turned off during an erase. Note 1: When a Bulk Erase Program Memory command is executed, the entire program Flash memory and configuration memory will be erased.  2015-2016 Microchip Technology Inc. DS40001819B-page 96...
  • Page 97 The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. parameter for specific trip point voltages.  2015-2016 Microchip Technology Inc. DS40001819B-page 97...
  • Page 98 See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, “PIC16(L)F170X Memory Programming Specification” (DS41683).  2015-2016 Microchip Technology Inc. DS40001819B-page 98...
  • Page 99 11 0000 1000 1110 (308E) PIC16F1778 11 0000 1000 1111 (308F) PIC16F1779 11 0000 1001 0000 (3090) PIC16LF1777 11 0000 1001 0001 (3091) PIC16LF1778 11 0000 1001 0010 (3092) PIC16LF1779 11 0000 1001 0011 (3093)  2015-2016 Microchip Technology Inc. DS40001819B-page 99...
  • Page 100 REVID: REVISION ID REGISTER REV<13:8> bit 13 bit 8 REV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-0 REV<13:0>: Revision ID bits  2015-2016 Microchip Technology Inc. DS40001819B-page 100...
  • Page 101: Oscillator Module (With Fail-Safe Clock Monitor)

    The INTOSC internal oscillator block produces low, medium, high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2015-2016 Microchip Technology Inc. DS40001819B-page 101...
  • Page 102 31 kHz 31 kHz Source 0000 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Inputs Outputs PLLEN or FOSC<2:0> IRCF PRIMUX PLLMUX SPLLEN =100 =1110 ≠ 1110 ≠ ≠  2015-2016 Microchip Technology Inc. DS40001819B-page 102...
  • Page 103 EC mode has three power modes to select from through quartz crystal and ceramic resonators, respectively. Configuration Words: • ECH – High power, 4-32 MHz • ECM – Medium power, 0.5-4 MHz • ECL – Low power, 0-0.5 MHz  2015-2016 Microchip Technology Inc. DS40001819B-page 103...
  • Page 104 In order to minimize latency between external oscillator • AN949, “Making Your Oscillator Work” start-up and code execution, the Two-Speed Clock (DS00949) Start-up mode can be selected (see Section 5.4 “Two-Speed Clock Start-up Mode”).  2015-2016 Microchip Technology Inc. DS40001819B-page 104...
  • Page 105 Refer to Section 5.3 Low-Power External Oscillators” for more information. “Clock Switching” (DS01288) FIGURE 5-5: QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) Rev. 10-000061A 7/30/2013 ® SOSCI To Internal Logic 32.768 kHz Quartz Crystal SOSCO  2015-2016 Microchip Technology Inc. DS40001819B-page 105...
  • Page 106 Oscillator) is uncalibrated and operates at • component tolerances 31 kHz. • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.  2015-2016 Microchip Technology Inc. DS40001819B-page 106...
  • Page 107 • Fail-Safe Clock Monitor (FSCM) (MFIOFR) of the OSCSTAT register indicates when the The Low-Frequency Internal Oscillator Ready bit MFINTOSC is running. (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.  2015-2016 Microchip Technology Inc. DS40001819B-page 107...
  • Page 108 Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.  2015-2016 Microchip Technology Inc. DS40001819B-page 108...
  • Page 109 Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables Section 36.0 “Electrical Specifications”.  2015-2016 Microchip Technology Inc. DS40001819B-page 109...
  • Page 110 2-cycle Sync Running LFINTOSC   IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC  IRCF <3:0> System Clock  2015-2016 Microchip Technology Inc. DS40001819B-page 110...
  • Page 111 In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator.  2015-2016 Microchip Technology Inc. DS40001819B-page 111...
  • Page 112 31 kHz 1 cycle of each Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) PLL inactive. Note 1: Section 36.0 “Electrical Specifications”.  2015-2016 Microchip Technology Inc. DS40001819B-page 112...
  • Page 113 (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC OSC1 1022 1023 OSC2 Program Counter PC - N PC + 1 System Clock  2015-2016 Microchip Technology Inc. DS40001819B-page 113...
  • Page 114 The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2015-2016 Microchip Technology Inc. DS40001819B-page 114...
  • Page 115 Clock Monitor Output Failure Detected OSCFIF Test Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity.  2015-2016 Microchip Technology Inc. DS40001819B-page 115...
  • Page 116 00 = Clock determined by FOSC<2:0> in Configuration Words Duplicate frequency derived from HFINTOSC. Note 1: 32 MHz when SPLLEN bit is set. Refer to Section 5.2.2.6 “32 MHz Internal Oscillator Frequency Selection”.  2015-2016 Microchip Technology Inc. DS40001819B-page 116...
  • Page 117 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate  2015-2016 Microchip Technology Inc. DS40001819B-page 117...
  • Page 118 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 MCLRE PWRTE WDTE<1:0> FOSC<2:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 118...
  • Page 119: Resets

    ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE /MCLR Sleep Time-out Device Reset Power-on Reset Active Brown-out Power-up Reset Timer LFINTOSC PWRTE LPBOR Reset Table 6.2.1 for BOR active conditions. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 119...
  • Page 120 Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.  2015-2016 Microchip Technology Inc. DS40001819B-page 120...
  • Page 121 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive BOREN<1:0> bits are located in Configuration Words. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 121...
  • Page 122 See Section 11.1 “PORTA Regis- device will begin execution after 10 F cycles (see ters” for more information. Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel.  2015-2016 Microchip Technology Inc. DS40001819B-page 122...
  • Page 123 PIC16(L)F1777/8/9 FIGURE 6-3: RESET START-UP SEQUENCE Internal POR PWRT Power-up Timer MCLR MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-up Timer Oscillator Internal Oscillator Oscillator External Clock (EC) CLKIN  2015-2016 Microchip Technology Inc. DS40001819B-page 123...
  • Page 124 Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2015-2016 Microchip Technology Inc. DS40001819B-page 124...
  • Page 125 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2015-2016 Microchip Technology Inc. DS40001819B-page 125...
  • Page 126 — — BORRDY PCON STKOVF STKUNF — RWDT RMCLR STATUS — — — WDTCON — — WDTPS<4:0> SWDTEN Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2015-2016 Microchip Technology Inc. DS40001819B-page 126...
  • Page 127: Interrupts

    A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Rev. 10-000010A 1/13/2014 TMR0IF Wake-up (If in Sleep mode) TMR0IE INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF Interrupt (TMR1IE) PIE1<0> IOCIE to CPU PEIE PIRn<7> PIEn<7>  2015-2016 Microchip Technology Inc. DS40001819B-page 127...
  • Page 128 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2015-2016 Microchip Technology Inc. DS40001819B-page 128...
  • Page 129 Interrupt PC-1 FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) Inst(0004h) Inst(0005h) Interrupt PC-1 FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) Inst(0004h)  2015-2016 Microchip Technology Inc. DS40001819B-page 129...
  • Page 130 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 36.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2015-2016 Microchip Technology Inc. DS40001819B-page 130...
  • Page 131 ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.  2015-2016 Microchip Technology Inc. DS40001819B-page 131...
  • Page 132 Global Enable bit, GIE, of the INTCON register. User software should ensure appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 132...
  • Page 133 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 133...
  • Page 134 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 134...
  • Page 135 0 = CLC2 interrupt disabled bit 0 CLC1IE: CLC1 Interrupt Enable bit 1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 135...
  • Page 136 0 = Disables the Timer6 to T6PR match interrupt bit 0 TMR4IE: TMR4 to T4PR Match Interrupt Enable bit 1 = Enables the Timer4 to T4PR match interrupt 0 = Disables the Timer4 to T4PR match interrupt  2015-2016 Microchip Technology Inc. DS40001819B-page 136...
  • Page 137 0 = Disables the Comparator C6 interrupt bit 0 C5IE: Comparator C5 Interrupt Enable bit 1 = Enables the Comparator C5 interrupt 0 = Disables the Comparator C5 interrupt PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 137...
  • Page 138 PWM6IE: PWM6 Interrupt Enable bit 1 = PWM6 interrupt enabled 0 = PWM6 interrupt disabled bit 0 PWM5IE: PWM5 Interrupt Enable bit 1 = PWM5 interrupt enabled 0 = PWM5 interrupt disabled PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 138...
  • Page 139 Global Enable bit, GIE, of the INTCON register. User software should ensure appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 139...
  • Page 140 Global Enable bit, GIE, of the INTCON register. User software should ensure appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 140...
  • Page 141 Global Enable bit, GIE, of the INTCON register. User software should ensure appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2016 Microchip Technology Inc. DS40001819B-page 141...
  • Page 142 TMR6IF: TMR6 to T6PR Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR4IF: TMR4 to T4PR Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2015-2016 Microchip Technology Inc. DS40001819B-page 142...
  • Page 143 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 C5IF: Comparator C5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 143...
  • Page 144 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 PWM5IF: PWM5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 144...
  • Page 145 COG3IF C8IF C7IF C6IF C5IF PIR6 — — — — PWM12IF PWM11IF PWM6IF PWM5IF — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. Legend: PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 145...
  • Page 146: Power-Down Mode (Sleep)

    Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 17.0 “5-Bit Digital-to-Analog Converter (DAC) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2015-2016 Microchip Technology Inc. DS40001819B-page 146...
  • Page 147 . This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4 “Two-Speed Clock Start-up Mode” GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.  2015-2016 Microchip Technology Inc. DS40001819B-page 147...
  • Page 148 The Low-Power Sleep mode is beneficial for applica- tions that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.  2015-2016 Microchip Technology Inc. DS40001819B-page 148...
  • Page 149 0 = Normal Power mode enabled in Sleep Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. PIC16F1777/8/9 only. Note 1: Section 36.0 “Electrical Specifications”.  2015-2016 Microchip Technology Inc. DS40001819B-page 149...
  • Page 150 — — — VREGPM Reserved WDTCON — — WDTPS<4:0> SWDTEN — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. Legend: PIC16(L)F1777/9 only. Note 1: Unimplemented on PIC16LF1777/8/9.  2015-2016 Microchip Technology Inc. DS40001819B-page 150...
  • Page 151: Watchdog Timer (Wdt)

    • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000141A 7/30/2013 WDTE<1:0> = 01 SWDTEN 23- it Programmable WDTE<1:0> = 11 LFINTOSC Time-out Prescaler WDT WDTE<1:0> = 10 Sleep WDTPS<4:0>  2015-2016 Microchip Technology Inc. DS40001819B-page 151...
  • Page 152 Active Disabled Disabled Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds.  2015-2016 Microchip Technology Inc. DS40001819B-page 152...
  • Page 153 Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected  2015-2016 Microchip Technology Inc. DS40001819B-page 153...
  • Page 154 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 154...
  • Page 155 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.  2015-2016 Microchip Technology Inc. DS40001819B-page 155...
  • Page 156: Flash Program Memory Control

    MSB of the Table 10-1 for Erase Row size and the number of address is written to the PMADRH register and the LSB write latches for Flash program memory. is written to the PMADRL register.  2015-2016 Microchip Technology Inc. DS40001819B-page 156...
  • Page 157 NOPs. NOP execution forced This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set. Data read now in PMDATH:PMDATL Read Operation  2015-2016 Microchip Technology Inc. DS40001819B-page 157...
  • Page 158 10-1) ; Ignored (Figure 10-1) MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2015-2016 Microchip Technology Inc. DS40001819B-page 158...
  • Page 159 Instruction fetched ignored NOP execution forced instruction. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. Unlock Sequence  2015-2016 Microchip Technology Inc. DS40001819B-page 159...
  • Page 160 (WREN = 1) Unlock Sequence (See Note 1) CPU stalls while Erase operation completes (2 ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) Erase Operation Note 1: See Figure 10-3.  2015-2016 Microchip Technology Inc. DS40001819B-page 160...
  • Page 161 ; NOP instructions are forced as processor starts ; row erase of program memory. ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction PMCON1,WREN ; Disable writes INTCON,GIE ; Enable interrupts  2015-2016 Microchip Technology Inc. DS40001819B-page 161...
  • Page 162 Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing.  2015-2016 Microchip Technology Inc. DS40001819B-page 162...
  • Page 163 FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES Rev. 10-000004A 7/30/2013 PMADRH PMADRL PMDATH PMDATL Program Memory Write Latches Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31 PMADRL<4:0> Addr Addr Addr Addr 000h 0000h 0001h...
  • Page 164 (FREE = 0) Disable No delay when writing to Write/Erase Operation Program Memory Latches (WREN = 0) Load Write Latches Only (LWLO = 1) Re-enable Interrupts (GIE = 1) Increment Address (PMADRH:PMADRL++) Write Operation  2015-2016 Microchip Technology Inc. DS40001819B-page 164...
  • Page 165 ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction PMCON1,WREN ; Disable writes INTCON,GIE ; Enable interrupts  2015-2016 Microchip Technology Inc. DS40001819B-page 165...
  • Page 166 RAM image Erase Operation (See Note 2) Write Operation Use RAM image (See Note 3) Modify Operation Note 1: See Figure 10-1. 2: See Figure 10-4. 3: See Figure 10-6.  2015-2016 Microchip Technology Inc. DS40001819B-page 166...
  • Page 167 10-2) INTCON,GIE ; Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2015-2016 Microchip Technology Inc. DS40001819B-page 167...
  • Page 168 Flash Program Memory Read Operation (See Note 1) PMDAT = RAM image ? Fail Verify Operation Last word ? Verify Operation Note 1: See Figure 10-1.  2015-2016 Microchip Technology Inc. DS40001819B-page 168...
  • Page 169 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address  2015-2016 Microchip Technology Inc. DS40001819B-page 169...
  • Page 170 ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address Unimplemented, read as ‘1’. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 170...
  • Page 171 The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1).  2015-2016 Microchip Technology Inc. DS40001819B-page 171...
  • Page 172 FOSC<2:0> CONFIG2 13:8 — — DEBUG LPBOR BORV STVREN PLLEN — — — — PPS1WAY WRT<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 172...
  • Page 173: I/O Ports

    A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1.  2015-2016 Microchip Technology Inc. DS40001819B-page 173...
  • Page 174 CLRF PORTA ;Init PORTA rate possible. BANKSEL LATA ;Data Latch CLRF LATA BANKSEL ANSELA CLRF ANSELA ;digital I/O BANKSEL TRISA MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs  2015-2016 Microchip Technology Inc. DS40001819B-page 174...
  • Page 175 These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 175...
  • Page 176 ‘0’ = Bit is cleared bit 7-0 LATA<7:0>: RA<7:0> Output Latch Value bits Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return Note 1: of actual I/O pin values.  2015-2016 Microchip Technology Inc. DS40001819B-page 176...
  • Page 177 Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.  2015-2016 Microchip Technology Inc. DS40001819B-page 177...
  • Page 178 ‘0’ = Bit is cleared bit 7-0 INLVLA<7:0>: PORTA Input Level Select bits For RA<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds  2015-2016 Microchip Technology Inc. DS40001819B-page 178...
  • Page 179 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2015-2016 Microchip Technology Inc. DS40001819B-page 179...
  • Page 180 The output drivers on RB1 and RB0 are capable of sourcing and sinking up to 100 mA. This extra drive capacity can be enabled and disabled with the control bits in the HIDRVB register (Register 11-17).  2015-2016 Microchip Technology Inc. DS40001819B-page 180...
  • Page 181 ‘0’ = Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values.  2015-2016 Microchip Technology Inc. DS40001819B-page 181...
  • Page 182 Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.  2015-2016 Microchip Technology Inc. DS40001819B-page 182...
  • Page 183 ‘0’ = Bit is cleared bit 7-0 INLVLB<7:0>: PORTB Input Level Select bits For RB<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds  2015-2016 Microchip Technology Inc. DS40001819B-page 183...
  • Page 184 TRISB2 TRISB1 TRISB0 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Legend: PORTB.  2015-2016 Microchip Technology Inc. DS40001819B-page 184...
  • Page 185 These inputs are active when the I/O pin is set for Analog mode using the ANSELC register. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 185...
  • Page 186 ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output  2015-2016 Microchip Technology Inc. DS40001819B-page 186...
  • Page 187 Unimplemented: Read as ‘0’ When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 187...
  • Page 188 7-0 ODC<7:0>: PORTC Open-Drain Enable bits For RC<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current)  2015-2016 Microchip Technology Inc. DS40001819B-page 188...
  • Page 189 ‘0’ = Bit is cleared bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits For RC<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds  2015-2016 Microchip Technology Inc. DS40001819B-page 189...
  • Page 190 TRISC2 TRISC1 TRISC0 WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Legend: PORTC.  2015-2016 Microchip Technology Inc. DS40001819B-page 190...
  • Page 191 These inputs are active when the I/O pin is set for that pin. Analog mode using the ANSELD register. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 191...
  • Page 192 ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output  2015-2016 Microchip Technology Inc. DS40001819B-page 192...
  • Page 193 0 = Digital I/O. Pin is assigned to port or digital special function. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 193...
  • Page 194 7-0 ODD<7:0>: PORTD Open-Drain Enable bits For RD<7:0> pins 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current)  2015-2016 Microchip Technology Inc. DS40001819B-page 194...
  • Page 195 ‘0’ = Bit is cleared bit 7-0 INLVLD<7:0>: PORTD Input Level Select bits For RD<7:0> pins 1 = Port pin digital input operates with ST thresholds 0 = Port pin digital input operates with TTL thresholds  2015-2016 Microchip Technology Inc. DS40001819B-page 195...
  • Page 196 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Legend: PORTD. PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 196...
  • Page 197 ‘0’ by user software. active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 197...
  • Page 198 These inputs are active when the I/O pin is set for Analog mode using the ANSELE register. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 198...
  • Page 199 TRISE<2:0>: RE<2:0> Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output TRISE<2:0> are not implemented on the PIC16(L)F1778. Note 1: Unimplemented, read as ‘1’.  2015-2016 Microchip Technology Inc. DS40001819B-page 199...
  • Page 200 When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. The ANSELE register is not implemented on the PIC16(L)F1778.  2015-2016 Microchip Technology Inc. DS40001819B-page 200...
  • Page 201 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) The ODCONE register is not implemented on the PIC16(L)F1778. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 201...
  • Page 202 WPUE3 WPUE2 WPUE1 WPUE0 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Legend: Unimplemented, read as ‘1’. Note 1: PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 202...
  • Page 203: Peripheral Pin Select (Pps) Module

    The notation “xxx” in the register name is Note: a place holder for the peripheral identifier. For example, CLC1PPS. FIGURE 12-1: SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS Peripheral abc RxyPPS Peripheral xyz RC7PPS xyzPPS  2015-2016 Microchip Technology Inc. DS40001819B-page 203...
  • Page 204 ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes PPSLOCK,PPSLOCKED ; restore interrupts INTCON,GIE  2015-2016 Microchip Technology Inc. DS40001819B-page 204...
  • Page 205 ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RxyPPS<5:0>: Pin Rxy Output Source Selection bits Selection code determines the output signal on the port pin. Table 12-2 for the selection codes  2015-2016 Microchip Technology Inc. DS40001819B-page 205...
  • Page 206 7-1 Unimplemented: Read as ‘0’ bit 0 PPSLOCKED: PPS Locked bit 1 = PPS is locked. PPS selections can not be changed. 0 = PPS is not locked. PPS selections can be changed.  2015-2016 Microchip Technology Inc. DS40001819B-page 206...
  • Page 207  PRG4 set rising PRG4RPPS 010100   PRG4set falling PRG4FPPS 010101     ADC trigger ADCACTPPS 001100 Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input. PIC16(L)F1777/9 only Note  2015-2016 Microchip Technology Inc. DS40001819B-page 207...
  • Page 208 All CLCs CLCIN1PPS 000001     All CLCs CLCIN2PPS 001110     All CLCs CLCIN3PPS 001111 Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input. PIC16(L)F1777/9 only Note  2015-2016 Microchip Technology Inc. DS40001819B-page 208...
  • Page 209    COG2C — — — 001011     COG2B 001010 TRIS control is overridden by the peripheral as required. Note 1: Unsupported peripherals will output a ‘0’. PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 209...
  • Page 210   LC1_out 000001         LATxy 000000 TRIS control is overridden by the peripheral as required. Note 1: Unsupported peripherals will output a ‘0’. PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 210...
  • Page 211 PRG1RPPS<5:0> — — PRG1FPPS PRG1FPPS<5:0> — — PRG2RPPS PRG2RPPS<5:0> — — PRG2FPPS PRG2FPPS<5:0> — — PRG3RPPS PRG3RPPS<5:0> — — PRG3FPPS PRG3FPPS<5:0> — — PRG4RPPS PRG4RPPS<5:0> — — PRG4FPPS PRG4FPPS<5:0> — — CLC1IN0PPS CLCIN0PPS<5:0>  2015-2016 Microchip Technology Inc. DS40001819B-page 211...
  • Page 212 SSPDATPPS SSPDATPPS<5:0> — — SSPSSPPS SSPSSPPS<5:0> — — RXPPS RXPPS<5:0> — — CKPPS CKPPS<5:0> — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module. Legend: PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 212...
  • Page 213: Interrupt-On-Change

    Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep.  2015-2016 Microchip Technology Inc. DS40001819B-page 213...
  • Page 214 Q4Q1 edge detect to data bus data bus = IOCAFx IOCAPx 0 or 1 write IOCAFx IOCIE IOC interrupt to CPU core from all other IOCnFx individual pin detectors Q4Q1 Q4Q1 Q4Q1 Q4Q1  2015-2016 Microchip Technology Inc. DS40001819B-page 214...
  • Page 215 IOCAN<7:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 215...
  • Page 216 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 216...
  • Page 217 Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change.  2015-2016 Microchip Technology Inc. DS40001819B-page 217...
  • Page 218 Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change.  2015-2016 Microchip Technology Inc. DS40001819B-page 218...
  • Page 219 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCEFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 2-0 Unimplemented: Read as ‘0’  2015-2016 Microchip Technology Inc. DS40001819B-page 219...
  • Page 220 TRISC0 TRISE — — — — — TRISE2 TRISE1 TRISE0 — unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. Legend: Unimplemented, read as ‘1’. Note 1: Unimplemented on PIC16(L)F1778.  2015-2016 Microchip Technology Inc. DS40001819B-page 220...
  • Page 221: Fixed Voltage Reference (Fvr)

    DAC and comparator module. Reference Section 17.0 “5-Bit Digi- tal-to-Analog Converter (DAC) Module” for additional Section 19.0 “Comparator Module” information.  2015-2016 Microchip Technology Inc. DS40001819B-page 221...
  • Page 222 BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled All PIC16F1773/6 devices, when The device runs off of the ULP regulator when in Sleep mode VREGPM = 1 and not in Sleep  2015-2016 Microchip Technology Inc. DS40001819B-page 222...
  • Page 223 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> Shaded cells are not used with the Fixed Voltage Reference. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 223...
  • Page 224: Temperature Indicator Module

    The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2015-2016 Microchip Technology Inc. DS40001819B-page 224...
  • Page 225 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDFVR<1:0> ADFVR<1:0> Legend: Shaded cells are unused by the temperature indicator module.  2015-2016 Microchip Technology Inc. DS40001819B-page 225...
  • Page 226: Analog-To-Digital Converter (Adc) Module

    Inputs FVR_buffer1 Sample Circuit CHS<4:0> ADFM set bit ADIF complete 10-bit Result Write to bit GO/DONE GO/DONE start ADRESH ADRESL Enable Trigger Select TRIGSEL<5:0> ADON . . . Trigger Sources AUTO CONVERSION TRIGGER  2015-2016 Microchip Technology Inc. DS40001819B-page 226...
  • Page 227 • V + pin • V • FVR 2.048V • FVR 4.096V (Not available on LF devices) • V Section 16.0 “Analog-to-Digital Converter for more details on the Fixed Voltage (ADC) Module” Reference.  2015-2016 Microchip Technology Inc. DS40001819B-page 227...
  • Page 228 (THCD). ADRESH:ADRESL is loaded, GO bit is cleared, Set GO bit ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) Select channel (ACS bits)  2015-2016 Microchip Technology Inc. DS40001819B-page 228...
  • Page 229 7 bit 0 bit 7 bit 0 10-bit ADC Result Unimplemented: Read as ‘0’ (ADFM = 1) bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit ADC Result  2015-2016 Microchip Technology Inc. DS40001819B-page 229...
  • Page 230 ADC module is turned off, although the ADON bit remains set. PWM5 PR/PH/OF/DC5_match PWM6 PR/PH/OF/DC6_match PR/PH/OF/DC10_match PWM10 PWM11 PR/PH/OF/DC11_match PWM12 PR/PH/OF/DC12_match ADCACT ADCACTPPS Pin PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 230...
  • Page 231 Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 16.4 “ADC Acquisi- tion Requirements”.  2015-2016 Microchip Technology Inc. DS40001819B-page 231...
  • Page 232 001010 = AN10 001001 = AN9 001000 = AN8 000111 = AN7 000110 = AN6 000101 = AN5 000100 = AN4 000011 = AN3 000010 = AN2 000001 = AN1 000000 = AN0  2015-2016 Microchip Technology Inc. DS40001819B-page 232...
  • Page 233 Section 15.0 “Temperature Indicator Module” See Section 18.0 “10-bit Digital-to-Analog Converter (DAC) Module” for more information. Input source is switched off when op amp override is forcing tri-state. See Section 29.3 “Override Control” PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 233...
  • Page 234 + is connected to V When selecting the V + pin as the source of the positive reference, be aware that a minimum voltage Note 1: specification exists. See Table 36-16: ADC Conversion Requirements for details.  2015-2016 Microchip Technology Inc. DS40001819B-page 234...
  • Page 235 000011 = Timer1 – T1_overflow 000010 = Timer0 – T0_overflow 000001 = ADCACT – ADCACTPPS Pin 000000 = No Auto-conversion Trigger selected This is a rising edge sensitive input for all sources. Note 1: PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 235...
  • Page 236 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2015-2016 Microchip Technology Inc. DS40001819B-page 236...
  • Page 237 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2015-2016 Microchip Technology Inc. DS40001819B-page 237...
  • Page 238 2: The charge holding capacitor (C ) is not discharged after each conversion. HOLD 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2015-2016 Microchip Technology Inc. DS40001819B-page 238...
  • Page 239 Note 1: Refer to Table 36-4: I/O Ports (parameter D060). FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh 3FBh Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale Ref- Full-Scale Transition Ref+ Transition  2015-2016 Microchip Technology Inc. DS40001819B-page 239...
  • Page 240 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not Legend: used for the ADC module.  2015-2016 Microchip Technology Inc. DS40001819B-page 240...
  • Page 241: 5-Bit Digital-To-Analog Converter (Dac) Module

    DAC output value. The value of the individual resistors within the ladder can be found in Table 36-20: 10-bit Digital-to-Analog Converter (DAC) Specifications.  2015-2016 Microchip Technology Inc. DS40001819B-page 241...
  • Page 242 SOURCE + R<4:0> PSS<1:0> utput (To Comparator and Steps ADC Modules) OUT1 NSS<1:0> OUT2 Reserved SOURCE - FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® Module Buffered DAC Output Voltage – Reference Output Impedance  2015-2016 Microchip Technology Inc. DS40001819B-page 242...
  • Page 243 17.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the pin. • The REF<4:0> voltage reference control bits are cleared.  2015-2016 Microchip Technology Inc. DS40001819B-page 243...
  • Page 244 01 = V + pin 00 = V bit 1-0 NSS<1:0>: DAC Negative Source Select bits 11 = Reserved, do not use 10 = DACxREF1- (DAC7/8) or Reserved (DAC3/4) 01 = DACxREF0- 00 = AG  2015-2016 Microchip Technology Inc. DS40001819B-page 244...
  • Page 245 NSS<1:0> DAC8CON0 PSS<1:0> NSS<1:0> DAC3REF REF<4:0> DAC4REF REF<4:0> DAC7REF REF<4:0> DAC8REF REF<4:0> — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module. Legend: PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 245...
  • Page 246: 10-Bit Digital-To-Analog Converter (Dac) Module

    IF EN = 1     DACxR 9:0    DACx_output – ------------------------------- -  SOURCE SOURCE  SOURCE + = V +, or FVR_buffer2 SOURCE - = V SOURCE SS OR  2015-2016 Microchip Technology Inc. DS40001819B-page 246...
  • Page 247 DACxREFH DACxREFL write 1 to 10-bit Latch Reserved DACxLD bit (not visible to user) FVR_buffer2 SOURCE PSS<1:0> DACx_output 1024 To Peripherals Steps DACxOUT1 Reserved DACxOUT2 SOURCE NSS<1:0> Note 1: DAC5 only, DAC1/2 is Reserved.  2015-2016 Microchip Technology Inc. DS40001819B-page 247...
  • Page 248 18.6 Effects of a Reset A device Reset affects the following: • DAC is disabled • DAC output voltage is removed from the • The REF<9:0> reference selection bits are cleared  2015-2016 Microchip Technology Inc. DS40001819B-page 248...
  • Page 249 01 = DAC REF0+ 00 = V bit 1-0 NSS<1:0>: DAC Negative Source Select bit 11 = Reserved. Do not use. 10 = DACxREF1- (DAC5/6) or Reserved (DAC1/2) 01 = DACxREF0- 00 = A  2015-2016 Microchip Technology Inc. DS40001819B-page 249...
  • Page 250 DACxOUT1 = f(REF<9:0>) (See Equation 18-1) bit 5-0 Unimplemented: Read as ‘0’ When FM = 0 (right justified) bit 7-0 REF<7:0>: DAC Reference Voltage Output Select bits DACxOUT1 = f(REF<9:0>) (See Equation 18-1)  2015-2016 Microchip Technology Inc. DS40001819B-page 250...
  • Page 251 REF<x-1:0> (x Depends on FM bit) DACLD DAC5LD DAC2LD DAC1LD — — — — — — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DACx module. Legend: PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 251...
  • Page 252: Comparator Module

    The comparators available for this device are located in Table 19-1. TABLE 19-1: AVAILABLE COMPARATORS Device C1 C2 C3 C4 C5 C6 C7 C8 PIC16(L)F1778 ● ● ● ● ● ● PIC16(L)F1777/9 ● ● ● ● ● ● ● ●  2015-2016 Microchip Technology Inc. DS40001819B-page 252...
  • Page 253 CxON PCH<3:0> SYNC TRIS bit From Timer1 tmr1_clk sync_CxOUT When CxON = 0, the comparator will produce a ‘0’ at the output. Note 1: When CxON = 0, all multiplexer inputs are disconnected.  2015-2016 Microchip Technology Inc. DS40001819B-page 253...
  • Page 254 • ON bit of the CMxCON0 register must be set Note 1: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external out- puts are not latched.  2015-2016 Microchip Technology Inc. DS40001819B-page 254...
  • Page 255 TRIS bits must also be set to disable edge detection) the output drivers. • INTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register  2015-2016 Microchip Technology Inc. DS40001819B-page 255...
  • Page 256 COMPARATOR ZERO LATENCY FILTER OPERATION CxOUT From Comparator CxOUT From ZLF Output waiting for T to expire before an output change is allowed. has expired so output change of ZLF is immediate based on comparator output change.  2015-2016 Microchip Technology Inc. DS40001819B-page 256...
  • Page 257 = Leakage Current at the pin due to various junctions LEAKAGE = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage Note 1: See I/O Ports in Table 36-4: I/O Ports.  2015-2016 Microchip Technology Inc. DS40001819B-page 257...
  • Page 258 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous  2015-2016 Microchip Technology Inc. DS40001819B-page 258...
  • Page 259 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit  2015-2016 Microchip Technology Inc. DS40001819B-page 259...
  • Page 260 CxIN4- pin CxIN4- (OPA4OUT) pin 0100 CxIN3- (OPA2OUT) pin CxIN3- pin 0011 CxIN2- pin CxIN2- pin 0010 CxIN1- (OPA1OUT) pin CxIN1- (OPA3OUT) pin 0001 CxIN0- pin CxIN0- pin 0000 PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 260...
  • Page 261 1000 DAC3_out DAC7_out 0111 DAC2_out DAC6_out 0110 DAC1_out DAC5_out 0101 PRG2_out PRG4_out 0100 PRG1_out PRG3_out 0011 FVR_Buffer2 FVR_Buffer2 0010 CxIN1+ pin CxIN1+ pin 0001 CxIN0+ pin CxIN0+ pin 0000 PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 261...
  • Page 262 MC4OUT: Mirror Copy of C4OUT bit bit 2 MC3OUT: Mirror Copy of C3OUT bit bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 262...
  • Page 263 REF<4:0> DAC4REF REF<4:0> DAC7REF REF<4:0> DAC8REF REF<4:0> DAC1REFH REF<9:x> (x Depends on FM bit) — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Legend: PIC16LF1777/9 only. Note  2015-2016 Microchip Technology Inc. DS40001819B-page 263...
  • Page 264 TRISB3 TRISB2 TRISB1 TRISB0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISC — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Legend: PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 264...
  • Page 265: Zero-Cross Detection (Zcd) Module

    • Low EMI cycle switching FIGURE 20-2: SIMPLIFIED ZCD BLOCK DIAGRAM pullup optional pullup External current limiting resistor CPINV ZCD pin External series voltage pulldown source optional ZCDx_output Interrupt Sets ZCDIF flag INTP INTN Interrupt  2015-2016 Microchip Technology Inc. DS40001819B-page 265...
  • Page 266 The ZCDIF bit of the PIR3 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.  2015-2016 Microchip Technology Inc. DS40001819B-page 266...
  • Page 267      1 –  ----- - 0.047 radians ------------ -      2f  125.6 s T  ------------ - = 120   2f  2015-2016 Microchip Technology Inc. DS40001819B-page 267...
  • Page 268 SERIES R FOR V RANGE When External Signal is relative to V   V maxpeak V minpeak series cpinv R pulldown ------------------------------------------ ----------------------------------------------------------- -   – Z cpinv series 4 – 10  2015-2016 Microchip Technology Inc. DS40001819B-page 268...
  • Page 269 ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the ZCDEN bit of the ZCDCON register must be set to enable the ZCD module.  2015-2016 Microchip Technology Inc. DS40001819B-page 269...
  • Page 270 1 = ZCDIF bit is set on high-to-low OUT transition 0 = ZCDIF bit is unaffected by high-to-low OUT transition The EN bit has no effect when the ZCD Configuration bit is cleared. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 270...
  • Page 271 Page CONFIG2 13:8 — — DEBUG LPBOR BORV STVREN PLLEN — — — — PPS1WAY WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.  2015-2016 Microchip Technology Inc. DS40001819B-page 271...
  • Page 272: Timer0 Module

    TMR0 is written. FIGURE 21-1: BLOCK DIAGRAM OF THE TIMER0 Data Bus Set TMR0IF T0CKIPPS T0CKI Sync TMR0 Timer0 overflow TMR0SE TMR0CS 8-bit Prescaler PS<2:0>  2015-2016 Microchip Technology Inc. DS40001819B-page 272...
  • Page 273 Timer1 External Clock Requirements. 21.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 273...
  • Page 274 Timer0 Module Register 272* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 274...
  • Page 275: Timer1/3/5 Module With Gate Control

    Internal Clock T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2015-2016 Microchip Technology Inc. DS40001819B-page 275...
  • Page 276 T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 22-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN Clock Source LFINTOSC External Clocking on T1CKI Pin System Clock (F Instruction Clock (F  2015-2016 Microchip Technology Inc. DS40001819B-page 276...
  • Page 277 Mode”).  Counts When switching from synchronous to Note: asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2015-2016 Microchip Technology Inc. DS40001819B-page 277...
  • Page 278 The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 22-4 for timing details.  2015-2016 Microchip Technology Inc. DS40001819B-page 278...
  • Page 279 T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2015-2016 Microchip Technology Inc. DS40001819B-page 279...
  • Page 280 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2015-2016 Microchip Technology Inc. DS40001819B-page 280...
  • Page 281 DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N + 1 N + 2 Cleared by Set by hardware on Cleared by software software TMR1GIF falling edge of T1GVAL  2015-2016 Microchip Technology Inc. DS40001819B-page 281...
  • Page 282 T1G t1g_in T1CKI T1GVAL Timer1 N + 4 N + 1 N + 2 N + 3 Set by hardware on Cleared by Cleared by software software falling edge of T1GVAL TMR1GIF  2015-2016 Microchip Technology Inc. DS40001819B-page 282...
  • Page 283 Unimplemented: Read as ‘0’ bit 0 ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop Timer1 only. Reserved, do not use for Timer3 and Timer5. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 283...
  • Page 284 1-0 GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin  2015-2016 Microchip Technology Inc. DS40001819B-page 284...
  • Page 285 CS<1:0> CKPS<1:0> OSCEN SYNC — TxGCON GPOL GSPM GGO/ GVAL GSS<1:0> DONE — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 285...
  • Page 286: Timer2/4/6/8 Module

    PSYNC TMRx_postscaled Comparator Postscaler Sync (2 Clocks) OUTPS<3:0> CKSYNC Note 1: Signal to the CCP to trigger the PWM pulse See Section 22.5 for description of CCP interaction in the different TMR modes  2015-2016 Microchip Technology Inc. DS40001819B-page 286...
  • Page 287 • External Reset Source event that resets the timer. as an input to several other input modules: • The ADC module, as an Auto-conversion Trigger TMR2 is not cleared when T2CON is Note: • COG, as an auto-shutdown source written.  2015-2016 Microchip Technology Inc. DS40001819B-page 287...
  • Page 288 TMRxHLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug Freeze mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 288...
  • Page 289 Note 1: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h. When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.  2015-2016 Microchip Technology Inc. DS40001819B-page 289...
  • Page 290 4/7/2016 CKPS 0b010 OUTPS 0b0001 TMRx_clk TMRx TMRx_postscaled TMRxIF Note 1: Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles Cleared by software.  2015-2016 Microchip Technology Inc. DS40001819B-page 290...
  • Page 291 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2015-2016 Microchip Technology Inc. DS40001819B-page 291...
  • Page 292 PWM output is high then the duty the counter. cycle is also extended. FIGURE 23-5: HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001) Rev. 10-000 196B 5/30/201 4 MODE 0b00001 TMRx_clk TMRx_ers TMRx TMRx_postscaled PWM Duty Cycle PWM Output  2015-2016 Microchip Technology Inc. DS40001819B-page 292...
  • Page 293 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2015-2016 Microchip Technology Inc. DS40001819B-page 293...
  • Page 294 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2015-2016 Microchip Technology Inc. DS40001819B-page 294...
  • Page 295 Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2015-2016 Microchip Technology Inc. DS40001819B-page 295...
  • Page 296 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2015-2016 Microchip Technology Inc. DS40001819B-page 296...
  • Page 297 CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an exter- nal signal edge resets the timer before the match occurs.  2015-2016 Microchip Technology Inc. DS40001819B-page 297...
  • Page 298 FIGURE 23-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100) Rev. 10-000201B 4/7/2016 MODE 0b01100 TMRx_clk Instruction TMRx_ers TMRx TMRx_postscaled PWM Duty Cycle PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON.
  • Page 299 The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match.  2015-2016 Microchip Technology Inc. DS40001819B-page 299...
  • Page 300 FIGURE 23-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110) Rev. 10-000202B 4/7/2016 MODE 0b01110 TMRx_clk Instruction TMRx_ers TMRx TMRx_postscaled PWM Duty Cycle PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON.
  • Page 301 PRx value. While the timer is incre- menting, additional edges on the external Reset signal will not affect the CCP PWM.  2015-2016 Microchip Technology Inc. DS40001819B-page 301...
  • Page 302 FIGURE 23-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001) Rev. 10-000203A 4/7/2016 MODE 0b10001 TMRx_clk Instruction TMRx_ers TMRx TMRx_postscaled PWM Duty Cycle PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON.
  • Page 303 CCP PWM operation the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer.  2015-2016 Microchip Technology Inc. DS40001819B-page 303...
  • Page 304 FIGURE 23-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110) Rev. 10-000204A 4/7/2016 MODE 0b10110 TMR2_clk Instruction TMR2_ers TMRx 1 2 3 4 5 4 5 0 TMR2_postscaled PWM Duty ‘D3 Cycle PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON.
  • Page 305 When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep.  2015-2016 Microchip Technology Inc. DS40001819B-page 305...
  • Page 306 0100 HFINTOSC HFINTOSC HFINTOSC HFINTOSC 0011 Fosc Fosc Fosc Fosc 0010 Fosc/4 Fosc/4 Fosc/4 Fosc/4 0001 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T8INPPS 0000  2015-2016 Microchip Technology Inc. DS40001819B-page 306...
  • Page 307 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler In certain modes, the ON bit will be auto-cleared by hardware. See Note 1: Section 23.6 “Operation Examples”.  2015-2016 Microchip Technology Inc. DS40001819B-page 307...
  • Page 308 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affect- ing the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 308...
  • Page 309 Reserved TMR6_postscaled 00011 TMR4_postscaled Reserved TMR4_postscaled TMR4_postscaled 00010 Reserved TMR2_postscaled TMR2_postscaled TMR2_postscaled 00001 Pin selected byT2INPPS Pin selected by T4INPPS Pin selected by T6INPPS Pin selected by T6INPPS 00000 PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 309...
  • Page 310 — — — RSEL<4:0> T8HLT PSYNC CKPOL CKSYNC MODE<4:0> — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. Legend: Page provides register information. PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 310...
  • Page 311: Capture/Compare/Pwm Modules

    TRIS control bit. If the CCPx pin is configured as an output, Note: a write to the port can cause a capture condition.  2015-2016 Microchip Technology Inc. DS40001819B-page 311...
  • Page 312 In addition, the CCP output can be output to any pin clearing the EN bit of the CCPxCON register before with that pin’s PPS control. changing the prescaler.  2015-2016 Microchip Technology Inc. DS40001819B-page 312...
  • Page 313 TMR1L register pair and the CCPRxH:CCPRxL FIGURE 24-2: COMPARE MODE OPERATION BLOCK DIAGRAM Rev. 10-000 159B 9/5/201 4 To Peripherals CCPRxH CCPRxL set CCPxIF CCP x Output Comparator Logic TRIS Control RxyPPS TMR1H TMR1L MODE<3:0>  2015-2016 Microchip Technology Inc. DS40001819B-page 313...
  • Page 314 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the PPS controls. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more detail.  2015-2016 Microchip Technology Inc. DS40001819B-page 314...
  • Page 315 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base. 2. The alignment of the 10 bits from the CCPR register is determined by the FMT bit.  2015-2016 Microchip Technology Inc. DS40001819B-page 315...
  • Page 316 PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored.  2015-2016 Microchip Technology Inc. DS40001819B-page 316...
  • Page 317 Where the particular bits go is determined by the FMT bit of the CCPxCON register. If FMT = 0, the two Most Significant bits of the duty cycle value should be written to bits <1:0> of the CCPRxH register and the remaining  2015-2016 Microchip Technology Inc. DS40001819B-page 317...
  • Page 318 This output is available to the following peripherals: • ADC Trigger • COG • PRG • DSM • CLC • Op Amp override • Timer2/4/6/8 Reset • Any device pins  2015-2016 Microchip Technology Inc. DS40001819B-page 318...
  • Page 319 0011 = Capture mode: every rising or falling edge 0010 = Compare mode: toggle output on match 0001 = Compare mode: Toggle output and clear TMR1 on match 0000 = Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility)  2015-2016 Microchip Technology Inc. DS40001819B-page 319...
  • Page 320 MODE = PWM Mode && FMT = 0 CCPRxH<7:2>: Not used CCPRxH<1:0>: CCPW<9:8> – Pulse width Most Significant two bits MODE = PWM Mode && FMT = 1 CCPRxH<7:0>: CCPW<9:2> – Pulse width Most Significant eight bits  2015-2016 Microchip Technology Inc. DS40001819B-page 320...
  • Page 321 0111 = C7_sync_out 0110 = C6_sync_out 0101 = C5_sync_out 0100 = C4_sync_out 0011 = C3_sync_out 0010 = C2_sync_out 0001 = C1_sync_out 0000 = Pin selected with the CCPxPPS register PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 321...
  • Page 322 10 = CCP1 is based off Timer6 in PWM mode 01 = CCP1 is based off Timer4 in PWM mode 00 = CCP1 is based off Timer2 in PWM mode PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 322...
  • Page 323 10 = PWM3 is based off Timer6 in PWM mode 01 = PWM3 is based off Timer4 in PWM mode 00 = PWM3 is based off Timer2 in PWM mode PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 323...
  • Page 324 Timer8 Period Register 287* T8CON CKPS<2:0> OUTPS<3:0> TMR8 Timer8 Module Register Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. Page provides register information. PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 324...
  • Page 325: 10-Bit Pulse-Width Modulation (Pwm) Module

    PWM OUTPUT module for PWM operation, refer to Section 25.1.9 Period “Setup for PWM Operation using PWMx Output Pins”. Pulse Width TMR2 = T2PR TMR2 = PWM x DCH<7:0>:PWM x DCL<7:6> TMR2 = 0  2015-2016 Microchip Technology Inc. DS40001819B-page 325...
  • Page 326 Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.   4 T    PWM Period T2PR (TMR2 Prescale Value) = 1/F Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 326...
  • Page 327 Refer to Section 5.0 “Oscillator Module (with for additional details. Fail-Safe Clock Monitor)” 25.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states.  2015-2016 Microchip Technology Inc. DS40001819B-page 327...
  • Page 328 6 may be ignored. given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs.  2015-2016 Microchip Technology Inc. DS40001819B-page 328...
  • Page 329 OUT: PWM module output level when bit is read. bit 4 POL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as ‘0’  2015-2016 Microchip Technology Inc. DS40001819B-page 329...
  • Page 330 7-6 DC<1:0>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register. bit 5-0 Unimplemented: Read as ‘0’  2015-2016 Microchip Technology Inc. DS40001819B-page 330...
  • Page 331 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 331...
  • Page 332: 16-Bit Pulse-Width Modulation (Pwm) Module

    16-bt Latch 16-bt Latch PWMxPR PWMxPH PWMxOF PWMxDC Note 1: A PWM module cannot trigger from its own offset match event. The input corresponding to a PWM module’s own offset match is reserved.  2015-2016 Microchip Technology Inc. DS40001819B-page 332...
  • Page 333 PORT ODCON bits. 26.1.2 PWMx Output Polarity The output polarity is inverted by setting the POL bit of the PWMxCON register. The polarity control affects the PWM output even when the module is not enabled.  2015-2016 Microchip Technology Inc. DS40001819B-page 333...
  • Page 334 PWMxTMR value above which no phase Writes to PWMxOUT will have no effect in this mode. matches can occur. A detailed timing diagram for Center Aligned mode is shown in Figure 26-7.  2015-2016 Microchip Technology Inc. DS40001819B-page 334...
  • Page 335 FIGURE 26-4: STANDARD PWM MODE TIMING DIAGRAM Rev. 10-000142A 9/5/2013 Period Duty Cycle Phase PWMxCLK PWMxPR PWMxPH PWMxDC PWMxTMR PWMxOUT FIGURE 26-5: SET ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000143A 9/5/2013 Period Phase PWMxCLK PWMxPR PWMxPH PWMxTMR PWMxOUT...
  • Page 336 FIGURE 26-6: TOGGLE ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000144A 9/5/2013 Period Phase PWMxCLK PWMxPR PWMxPH PWMxTMR PWMxOUT FIGURE 26-7: CENTER ALIGNED PWM MODE TIMING DIAGRAM Rev. 10-000 145A 4/22/201 4 Period Duty Cycle PWMxCLK PWMxPR PWMxDC PWMxTMR PWMxOUT...
  • Page 337 PWMxTMR continues to count. The next master OF_match event resets the slave PWMxTMR back to 1 to repeat the cycle. Slave period events that occur before the master’s OF_match event  2015-2016 Microchip Technology Inc. DS40001819B-page 337...
  • Page 338 FIGURE 26-8: INDEPENDENT RUN MODE TIMING DIAGRAM Rev. 10-000 146B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR PWMxPH PWMxDC PWMxOF PWMxTMR PWMxOUT OFx_match PHx_match DCx_match PRx_match PWMyTMR PWMyPR PWMyPH PWMyDC PWMyOUT Note: PWMx = Master, PWMy = Slave...
  • Page 339 FIGURE 26-9: SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev. 10-000 147B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR PWMxPH PWMxDC PWMxOF PWMxTMR PWMxOUT OFx_match PWMyTMR PWMyPR PWMyPH PWMyDC PWMyOUT Note: Master = PWMx, Slave = PWMy...
  • Page 340 FIGURE 26-10: ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM Rev. 10-000 148B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR PWMxPH PWMxDC PWMxOF PWMxTMR PWMxOUT OFx_match PWMyTMR PWMyPR PWMyPH PWMyDC PWMyOUT Note: Master = PWMx, Slave = PWMy...
  • Page 341 FIGURE 26-11: CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM Rev. 10-000 149B 7/8/201 5 Period Duty Cycle Phase Offset PWMxCLK PWMxPR PWMxPH PWMxDC PWMxOF PWMxTMR PWMxOUT OFx_match PWMyTMR PWMyPR PWMyPH PWMyDC PWMyOUT Note: Master= PWMx, Slave=PWMy...
  • Page 342 FIGURE 26-12: OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM Rev. 10-000 150B 7/9/201 5 Period Duty Cycle Offset PWMxCLK PWMxPR PWMxDC PWMxOF PWMxTMR PWMxOUT OFx_match PHx_match DCx_match PRx_match PWMyTMR PWMyPR PWMyDC PWMyOUT Note: Master = PWMx, Slave = PWMy...
  • Page 343 FIGURE 26-13: OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM Rev. 10-000 151B 7/9/201 5 Period Duty Cycle Offset PWMxCLK PWMxPR PWMxDC PWMxOF PWMxTMR PWMxOUT OF5_match PH5_match DC5_match PR5_match PWMyTMR PWMyPR PWMyDC PWMyOUT Note: Master = PWMx, Slave = PWMy...
  • Page 344 2: If the LDA bit is set at the same time as PWMxTMR = PWMxPR, the LDA bit is ignored until the next period event. Such is the case when triggered reload is selected triggering event occurs simultaneously with the target’s period event  2015-2016 Microchip Technology Inc. DS40001819B-page 344...
  • Page 345 MODE<1:0>: PWM Mode Control bits 11 = Center Aligned mode 10 = Toggle On Match mode 01 = Set On Match mode 00 = Standard PWM mode bit 1-0 Unimplemented: Read as ‘0’  2015-2016 Microchip Technology Inc. DS40001819B-page 345...
  • Page 346 PRIF: Period Interrupt Flag bit 1 = Period Match Event occurred 0 = Period Match Event did not occur Bit is forced clear by hardware while module is disabled (EN = 0). Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 346...
  • Page 347 Unimplemented: Read as ‘0’ bit 1-0 CS<1:0>: Clock Source Select bits 11 = Reserved 10 = LFINTOSC (continues to operate during Sleep) 01 = HFINTOSC (continues to operate during Sleep) 00 = FOSC  2015-2016 Microchip Technology Inc. DS40001819B-page 347...
  • Page 348 This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing arming Note 1: event. The source corresponding to a PWM module’s own LDx_trigger is reserved.  2015-2016 Microchip Technology Inc. DS40001819B-page 348...
  • Page 349 Unimplemented: Read as ‘0’ bit 1-0 OFS<1:0>: Offset Trigger Source Select bit 10 = OF11_match 01 = OF6_match 00 = OF5_match The source corresponding to the PWM module’s own OFx_match is reserved. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 349...
  • Page 350 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PH<7:0>: PWM Phase Low bits Lower eight bits of PWM phase count  2015-2016 Microchip Technology Inc. DS40001819B-page 350...
  • Page 351 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 DC<7:0>: PWM Duty Cycle Low bits Lower eight bits of PWM duty cycle count  2015-2016 Microchip Technology Inc. DS40001819B-page 351...
  • Page 352 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PR<7:0>: PWM Period Low bits Lower eight bits of PWM period count  2015-2016 Microchip Technology Inc. DS40001819B-page 352...
  • Page 353 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 OF<7:0>: PWM Offset Low bits Lower eight bits of PWM offset count  2015-2016 Microchip Technology Inc. DS40001819B-page 353...
  • Page 354 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TMR<7:0>: PWM Timer Low bits Lower eight bits of PWM timer counter  2015-2016 Microchip Technology Inc. DS40001819B-page 354...
  • Page 355 Mirror copy of each PWM module’s PWMxCON<5> bit bit 1 MPWM6OUT: PWM6 OUT bits Mirror copy of each PWM module’s PWMxCON<5> bit bit 0 MPWM5OUT: PWM5 OUT bits Mirror copy of each PWM module’s PWMxCON<5> bit PIC16(L)F1777/9 only. Note  2015-2016 Microchip Technology Inc. DS40001819B-page 355...
  • Page 356 PHIF DCIF PRIF PWM11CLKCON — PS<2:0> — — CS<1:0> PWM11LDCON — — — — LDS<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by PWM. Legend: PIC16(L)F1777/9 only. Note  2015-2016 Microchip Technology Inc. DS40001819B-page 356...
  • Page 357 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 WDTE<1:0> FOSC<2:0> MCLRE PWRTE — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 357...
  • Page 358 PIC16(L)F1777/8/9 NOTES:  2015-2016 Microchip Technology Inc. DS40001819B-page 358...
  • Page 359: Complementary Output Generator (Cog) Modules

    • Blanking control with independent rising and falling event blanking times • Auto-shutdown control with: - Independently selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control (high, low, off, and High-Z)  2015-2016 Microchip Technology Inc. DS40001819B-page 359...
  • Page 360 Full-Bridge Forward and Full-Bridge Reverse modes are selected by setting the MD<2:0> bits of the COGxCON0 register to ‘010’ and ‘011’, respectively. FIGURE 27-1: EXAMPLE OF FULL-BRIDGE APPLICATION Driver Driver COGxA Load COGxB Driver Driver COGxC COGxD  2015-2016 Microchip Technology Inc. DS40001819B-page 360...
  • Page 361 The Push-Pull configuration is shown in Figure 27-6. A typical Push-Pull waveform generated from a single CCP1 input is shown in Figure 27-11. Push-Pull mode is selected by setting the MD<2:0> bits of the COGxCON0 register to ‘101’.  2015-2016 Microchip Technology Inc. DS40001819B-page 361...
  • Page 362 FIGURE 27-2: SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, MD = 0) ASDAC<1:0> ‘1’ ‘0’ Hi-Z Reserved HFINTOSC COG_clock COGxA Fosc Fosc/4 SDATA POLA CS<1:0> STRA Rising Input Block ASDBD<1:0> clock ‘1’ src15 ‘0’ Reset Dominates Rising event sources Hi-Z Register 27-3 rising_event Register...
  • Page 363 FIGURE 27-3: SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, MD = 1) ASDAC<1:0> ‘1’ ‘0’ High-Z Reserved HFINTOSC COG_clock COGxA Fosc Fosc/4 SDATA POLA CS<1:0> STRA Rising Input Block ASDBD<1:0> clock ‘1’ src15 ‘0’ Reset Dominates Rising event sources High-Z Register 27-3 rising_event...
  • Page 364 FIGURE 27-4: SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: MD = 2, REVERSE: MD = 3) ASDAC<1:0> ‘1’ ‘0’ High-Z Reserved HFINTOSC COG_clock COGxA Fosc Fosc/4 Rising Dead-Band Block CS<1:0> Rising Input Block POLA ASDBD<1:0> clock clock signal_out ‘1’ src15 signal_in ‘0’...
  • Page 365 FIGURE 27-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, MD = 4) ASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC COG_clock COGxA Fosc Fosc/4 CS<1:0> Rising Input Block POLA ASDBD<1:0> Rising Dead-Band Block clock ‘1’ src15 clock ‘0’ Reset Dominates Rising event sources signal_out High-Z Register 27-3...
  • Page 366 FIGURE 27-6: SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, MD = 5) ASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC COG_clock COGxA Fosc Fosc/4 CS<1:0> Rising Input Block POLA ASDBD<1:0> Push-Pull clock ‘1’ src15 ‘0’ Reset Dominates Rising event sources High-Z Register 27-3 rising_event Register 27-4.
  • Page 367 (R/F)IS15 (rising/falling)_event (R/F)SIM15 src1 through src14 (R/F)IS1 through (R/F)IS14 (R/F)SIM1 through (R/F)SIM14 src0 (R/F)IS0 (R/F)SIM0 FIGURE 27-8: COG (RISING/FALLING) DEAD-BAND BLOCK (R/F)DBTS Synchronous clock Delay Cnt/Clr DBR<3:0> Asynchronous Delay Chain signal_out signal_in  2015-2016 Microchip Technology Inc. DS40001819B-page 367...
  • Page 368 HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY COG_clock Source CCP1 COGxA rising event dead band falling event dead band Phase Delay falling event dead band COGxB FIGURE 27-11: PUSH-PULL MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB  2015-2016 Microchip Technology Inc. DS40001819B-page 368...
  • Page 369 FIGURE 27-12: FULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB COGxC COGxD FIGURE 27-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE CCP1 COGxA falling event dead band COGxB COGxC COGxD  2015-2016 Microchip Technology Inc. DS40001819B-page 369...
  • Page 370 If the clock input is level sensitive, duty cycles less than 50% will exhibit erratic operation because the level sensitive clock will suppress the comparator feedback.  2015-2016 Microchip Technology Inc. DS40001819B-page 370...
  • Page 371 Shutdown override direction change from forward to reverse. The Inactive Inactive state modulated output is delayed for the rising event Inactive Active PWM signal dead-band time after a direction change from reverse to forward.  2015-2016 Microchip Technology Inc. DS40001819B-page 371...
  • Page 372 Use turned off. The rising event dead-band time starts Equation 27-1 to calculate blanking times. when the rising_ event output goes true.  2015-2016 Microchip Technology Inc. DS40001819B-page 372...
  • Page 373 When the phase-delay count value is zero, phase delay is disabled and the phase-delay counter output is true, thereby, allowing the event signal to pass straight through to the complementary output driver flop.  2015-2016 Microchip Technology Inc. DS40001819B-page 373...
  • Page 374 Software Generated Shutdown forced low and high override levels but does apply to the PWM inactive state. Setting the ASE bit of the COGxASD0 register (Register 27-11) will force the COG into the shutdown state.  2015-2016 Microchip Technology Inc. DS40001819B-page 374...
  • Page 375 COG will restart from the auto-shutdown state automatically. The ASE bit will clear automatically and the COG will resume operation on the first rising event after all selected shutdown inputs go false.  2015-2016 Microchip Technology Inc. DS40001819B-page 375...
  • Page 376 FIGURE 27-15: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE CCP1 ARSEN Next rising event Shutdown input Next rising event Cleared in hardware Cleared in software ASDAC 2b00 2b00 ASDBD 2b00 COGxA COGxB Operating State NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SHUTDOWN...
  • Page 377 COG outputs to be used are set so that all are configured as inputs. The COG module will enable the output drivers as needed later. Clear the EN bit, if not already cleared.  2015-2016 Microchip Technology Inc. DS40001819B-page 377...
  • Page 378 011 = COG outputs operate in Reverse Full-Bridge mode 010 = COG outputs operate in Forward Full-Bridge mode 001 = COG outputs operate in synchronous steered PWM mode 000 = COG outputs operate in steered PWM mode  2015-2016 Microchip Technology Inc. DS40001819B-page 378...
  • Page 379 0 = Active level of COGxB output is high bit 0 POLA: COGxA Output Polarity Control bit 1 = Active level of COGxA output is low 0 = Active level of COGxA output is high  2015-2016 Microchip Technology Inc. DS40001819B-page 379...
  • Page 380 Pin selected with Pin selected with Pin selected with Pin selected with Pin selected with COG1PPS COG2PPS COG3PPS COG3PPS COG4PPS PIC16(L)F1777/9 only. Note PIC16(L)F1778 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 380...
  • Page 381 0 = Source <n> output high level will cause an immediate rising event RIS<n> = 0: Source <n> output has no effect on rising event Any combination of <n> bits can be selected. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 381...
  • Page 382 1 = Source <n> output is enabled as a falling event input 0 = Source <n> output has no effect on the falling event Any combination of <n> bits can be selected. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 382...
  • Page 383 0 = Source <n> output low level will cause an immediate falling event FIS<n> = 0: Source <n> output has no effect on falling event Any combination of <n> bits can be selected. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 383...
  • Page 384 01 = COGxA and COGxC are tri-stated when shutdown is active 00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown is active bit 1-0 Unimplemented: Read as ‘0’  2015-2016 Microchip Technology Inc. DS40001819B-page 384...
  • Page 385 Pin selected by Pin selected by Pin selected by Pin selected by Pin selected by COG1PPS COG2PPS COG3PPS COG3PPS COG4PPS Shutdown when source is high. Note PIC16(L)F1777/9 only. PIC16(L)F1778 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 385...
  • Page 386 0 = COGxA output is the static data level determined by the SDATA bit Steering is active only when the MD<1:0> bits of the COGxCON0 register = 00x. (See Register 27-1). Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 386...
  • Page 387 FDBS = 1: = Number of delay chain element periods to delay complementary output after falling event input FDBS = 0: = Number of COGx clock periods to delay complementary output after falling event input  2015-2016 Microchip Technology Inc. DS40001819B-page 387...
  • Page 388 ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 BLKF<5:0>: Falling Event Blanking Count Value bits Number of COGx clock periods to inhibit rising event inputs  2015-2016 Microchip Technology Inc. DS40001819B-page 388...
  • Page 389 ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PHF<5:0>: Falling Event Phase Delay Count Value bits = Number of COGx clock periods to delay falling event  2015-2016 Microchip Technology Inc. DS40001819B-page 389...
  • Page 390 RxyPPS — — RxyPPS<5:0> x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG. Legend: COG4 is available on PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 390...
  • Page 391: Configurable Logic Cell (Clc)

    LCx_in[2] CLCxPPS Logic Function CLCx Table 28-1. TRIS MODE<2:0> Interrupt LCx_in[35] LCx_in[36] LCx_in[37] INTP set bit INTN CLCxIF Interrupt Figure 28-2: Input Data Selection and Gating. Note 1: Figure 28-3: Programmable Logic Functions.  2015-2016 Microchip Technology Inc. DS40001819B-page 391...
  • Page 392 Timer5 overflow 101100 LCx_in[43] Timer3 overflow 101011 LCx_in[42] Timer1 overflow 101010 LCx_in[41] Timer0 overflow 101001 LCx_in[40] EUSART RX 101000 LCx_in[39] EUSART TX 100111 LCx_in[38] ZCD1_output 100110 LCx_in[37] MSSP1 SDO/SDA 100101 LCx_in[36] MSSP1 SCL/SCK 100100  2015-2016 Microchip Technology Inc. DS40001819B-page 392...
  • Page 393 • Gate 3: CLCxGLS2 (Register 28-9) • Gate 4: CLCxGLS3 (Register 28-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register.  2015-2016 Microchip Technology Inc. DS40001819B-page 393...
  • Page 394 CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2015-2016 Microchip Technology Inc. DS40001819B-page 394...
  • Page 395 (Same as Data GATE 1) Data GATE 3 LCx_in[37] D3S<4:0> (Same as Data GATE 1) Data GATE 4 LCx_in[0] (Same as Data GATE 1) Table 28-1. LCx_in[37] D4S<4:0> All controls are undefined at power-up. Note:  2015-2016 Microchip Technology Inc. DS40001819B-page 395...
  • Page 396 MODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R MODE<2:0>= 100 MODE<2:0>= 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R MODE<2:0>= 110 MODE<2:0>= 111  2015-2016 Microchip Technology Inc. DS40001819B-page 396...
  • Page 397 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR  2015-2016 Microchip Technology Inc. DS40001819B-page 397...
  • Page 398 0 G1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted  2015-2016 Microchip Technology Inc. DS40001819B-page 398...
  • Page 399 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 D3S<5:0>: CLCx Data 3 Input Selection bits Table 28-1.  2015-2016 Microchip Technology Inc. DS40001819B-page 399...
  • Page 400 0 = d1T is not gated into g1 bit 0 G1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = d1N is gated into g1 0 = d1N is not gated into g1  2015-2016 Microchip Technology Inc. DS40001819B-page 400...
  • Page 401 0 = d1T is not gated into g2 bit 0 G2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = d1N is gated into g2 0 = d1N is not gated into g2  2015-2016 Microchip Technology Inc. DS40001819B-page 401...
  • Page 402 0 = d1T is not gated into g3 bit 0 G3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = d1N is gated into g3 0 = d1N is not gated into g3  2015-2016 Microchip Technology Inc. DS40001819B-page 402...
  • Page 403 0 = d1T is not gated into g4 bit 0 G4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = d1N is gated into g4 0 = d1N is not gated into g4  2015-2016 Microchip Technology Inc. DS40001819B-page 403...
  • Page 404 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit  2015-2016 Microchip Technology Inc. DS40001819B-page 404...
  • Page 405 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISB TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISC — = unimplemented read as ‘0’. Shaded cells are not used for CLC module. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 405...
  • Page 406: Operational Amplifier (Opa) Modules

    - Forced unity gain FIGURE 29-1: OPAx MODULE BLOCK DIAGRAM OPAxIN0+ OPAx_out OPAxIN1+ Internal analog sources Register 29-4. PCH<1:0> OPAxIN0- OPAxIN1- Internal analog sources Register 29-3. NCH<1:0> ORM1 Internal override sources Register 29-2. ORS<1:0> ORM0 ORPOL  2015-2016 Microchip Technology Inc. DS40001819B-page 406...
  • Page 407 29-1) selects the Unity Gain mode. When unity gain is selected, the OPA output is connected to the inverting input and the OPAxIN pin is relinquished, releasing the pin for general purpose input and output.  2015-2016 Microchip Technology Inc. DS40001819B-page 407...
  • Page 408 10 = Op amp is forced to unity gain when override source is true. 01 = Op amp output is tri-stated when override source is true. 00 = Output override function is disabled.  2015-2016 Microchip Technology Inc. DS40001819B-page 408...
  • Page 409 PWM4_out PWM4_out PWM4_out 00101 PWM3_out PWM3_out PWM3_out PWM3_out 00100 CCP8_out CCP8_out CCP8_out CCP8_out 00011 CCP7_out CCP7_out CCP7_out CCP7_out 00010 00001 CCP2_out CCP2_out CCP2_out CCP2_out 00000 CCP1_out CCP1_out CCP1_out CCP1_out PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 409...
  • Page 410 DAC4_out DAC8_out DAC8_out 0101 DAC3_out DAC3_out DAC7_out DAC7_out 0100 DAC2_out DAC2_out DAC6_out DAC6_out 0011 DAC1_out DAC1_out DAC5_out DAC5_out 0010 OPA1IN1- OPA2IN1- OPA3IN1- OPA4IN1- 0001 OPA1IN0- OPA2IN0- OPA3IN0- OPA3IN0- 0000 PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 410...
  • Page 411 DAC4_out DAC8_out DAC8_out 0101 DAC3_out DAC3_out DAC7_out DAC7_out 0100 DAC2_out DAC2_out DAC6_out DAC6_out 0011 DAC1_out DAC1_out DAC5_out DAC5_out 0010 OPA1IN1+ OPA2IN1+ OPA3IN1+ OPA4IN1+ 0001 OPA1IN0+ OPA2IN0+ OPA3IN0+ OPA4IN0+ 0000 PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 411...
  • Page 412 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps. Legend:  2015-2016 Microchip Technology Inc. DS40001819B-page 412...
  • Page 413: Programmable Ramp Generator (Prg) Module

    • Any PWM output the one-shot period. Edge sensitive timing inputs that • Any I/O pin occur during the one-shot period will be ignored. Level  2015-2016 Microchip Technology Inc. DS40001819B-page 413...
  • Page 414 The RG module resets to a disabled condition. starts when the set_rising timing input goes true. The set_falling input dominates the set_rising input.  2015-2016 Microchip Technology Inc. DS40001819B-page 414...
  • Page 415 FIGURE 30-1: SIMPLIFIED PRG MODULE BLOCK DIAGRAM Rev. 10-000 220A 5/29/201 4 Table 30-4 ISET<4:0> RTSS<3:0> RPOL Set_rising Timing Sources (See Table 30-5) RAMPx_out peripherals PRGxR REDG PRGxRPPS Switch FTSS<3:0> Control FEDG Set_falling Timing Sources Voltage Sources (See Table 30-5) (See Table 30-3)
  • Page 416 FIGURE 30-2: SLOPE COMPENSATION (FALLING RAMP) TIMING DIAGRAM (MODE = 00) Rev. 10-000 223A 5/2/201 4 Init Running Init Running set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed voltage_ref RAMPx_out...
  • Page 417 FIGURE 30-3: ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 0, MODE = 01) Rev. 10-000 222A 4/29/201 4 Init Running Init Running REDG FEDG set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed voltage_ref RAMPx_out...
  • Page 418 FIGURE 30-4: ALTERNATING RISING/FALLING RAMP GENERATION TIMING DIAGRAM (OS = 1, MODE = 01) Rev. 10-000 226A 5/2/201 4 Init Running Init Running REDG FEDG set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed voltage_ref RAMPx_out...
  • Page 419 FIGURE 30-5: RISING RAMP GENERATION TIMING DIAGRAM (MODE = 10) Rev. 10-000 224A 5/2/201 4 Init Running Init Running set_rising set_falling one_shot sw1_closed sw2_closed sw3_closed RAMPx_out voltage_ref...
  • Page 420 ------------------------------------------- -   s  PWM Period ( Note: The setting for 0.5V/s is ISET<4:0> = 6 FIGURE 30-6: EXAMPLE SLOPE COMPENSATION CIRCUIT Rev. 10-000 221A 5/7/201 4 COGxOUTx CxINx- RGxIN OPAxOUT OPAxIN-  2015-2016 Microchip Technology Inc. DS40001819B-page 420...
  • Page 421 0 = Slope or Ramp function is not operating. All current source current source switches are open and capacitor discharge switch is closed. If EN = 0: This bit is forced to 0  2015-2016 Microchip Technology Inc. DS40001819B-page 421...
  • Page 422 FVR_buffer2 FVR_buffer2 0010 PRG1IN1/OPA2OUT PRG2IN1/OPA1OUT PRG3IN1/OPA4OUT PRG4IN1/OPA3OUT 0001 PRG1IN0/OPA1OUT PRG2IN0/OPA2OUT PRG3IN0/OPA3OUT PRG4IN0/OPA4OUT 0000 Input source is switched off when op amp override is forcing tri-state. See Note Section 29.3 “Override Control”. PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 422...
  • Page 423 Current source/sink setting and slope rate. See Table 30-4. TABLE 30-4: PROGRAMMABLE RAMP GENERATOR CURRENT SETTINGS Current Setting Slope Rate Current Setting Slope Rate ISET<4:0> ISET<4:0> (uA) (V/us) (uA) (V/us) 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95  2015-2016 Microchip Technology Inc. DS40001819B-page 423...
  • Page 424 ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 FTSS<3:0>: Set_falling Timing Source Select bits Table 30-5.  2015-2016 Microchip Technology Inc. DS40001819B-page 424...
  • Page 425 Reserved Reserved 0011 sync_C3OUT sync_C3OUT Reserved Reserved 0010 sync_C2OUT sync_C2OUT Reserved Reserved 0001 sync_C1OUT sync_C1OUT Reserved Reserved 0000 Input pin is selected with the PRGxRPPS or PRGxFPPS register. Note 1: PIC16(L)F1777/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 425...
  • Page 426 — — WPUC WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 WPUC7 WPUC6 — = unimplemented, read as ‘0’. Shaded cells are unused by the PRG module. Legend: PRG4 available on PIC16(L)F1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 426...
  • Page 427: Data Signal Modulator (Dsm)

    • Slew Rate Control Figure 31-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral. TABLE 31-1: AVAILABLE DSM MODULES Device DSM1 DSM2 DSM3 DSM4 PIC16(L)F1778 ● ● ● PIC16(L)F1777/9 ● ● ● ●  2015-2016 Microchip Technology Inc. DS40001819B-page 427...
  • Page 428 SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR CH<3:0> CHPPS Data Signal Modulator Carrier High Sources CARH Table 31-6 CHPOL SYNC MS<3:0> MODPPS Modulation Sources CHSYNC Table 31-6 OPOL CL<3:0> CLPPS SYNC Carrier Low Sources Table 31-7. CARL CLSYNC CLPOL  2015-2016 Microchip Technology Inc. DS40001819B-page 428...
  • Page 429 Figure 31-6 show timing diagrams of using various synchronization methods. 31.2 Modulator Signal Sources The modulator signal is selected by configuring the MS<4:0> bits of the MDxSRC register. Selections are shown in Table 31-6.  2015-2016 Microchip Technology Inc. DS40001819B-page 429...
  • Page 430 CARL Active Carrier State FIGURE 31-4: CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDx_out Active Carrier CARH CARH CARL both CARL both State  2015-2016 Microchip Technology Inc. DS40001819B-page 430...
  • Page 431 CARL State FIGURE 31-6: FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDx_out Active Carrier CARH CARL CARH CARL State  2015-2016 Microchip Technology Inc. DS40001819B-page 431...
  • Page 432 Modulated Output Polarity The modulated output signal provided on the MDxOUT pin can also be inverted. Inverting the modulated out- put signal is enabled by setting the OPOL bit of the MDxCON0 register.  2015-2016 Microchip Technology Inc. DS40001819B-page 432...
  • Page 433 Note 1: register bit, the bit value may not be valid for higher speed modulator or carrier signals. BIT must be selected as the modulation source in the MDSRC register for this operation.  2015-2016 Microchip Technology Inc. DS40001819B-page 433...
  • Page 434 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 MS<4:0> Modulation Source Selection bits Table 31-4 Table 31-5.  2015-2016 Microchip Technology Inc. DS40001819B-page 434...
  • Page 435 CCP7_out 00111 00111 CCP2_out CCP2_out 00110 00110 CCP1_out CCP1_out 00101 00101 SDO_OUT SDO_OUT 00100 00100 00011 00011 TX_out TX_out 00010 00010 MDxBIT MDxBIT 00001 00001 MDxMODPPS pin selection MDxMODPPS pin selection 00000 00000  2015-2016 Microchip Technology Inc. DS40001819B-page 435...
  • Page 436 Unimplemented: Read as ‘0’ bit 4-0 CH<4:0> Modulator Data High Carrier Selection bits Table 31-6. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 436...
  • Page 437 PWM9_out 01001 PWM4_out PWM4_out 01000 PWM3_out PWM3_out 00111 Reserved CCP8_out 00110 CCP7_out CCP7_out 00101 CCP2_out CCP2_out 00100 CCP1_out CCP1_out 00011 HFINTOSC HFINTOSC 00010 FOSC FOSC 00001 MDxMODPPS pin selection MDxMODPPS pin selection 00000  2015-2016 Microchip Technology Inc. DS40001819B-page 437...
  • Page 438 Unimplemented: Read as ‘0’ bit 4-0 CL<4:0> Modulator Data Low Carrier Selection bits Table 31-7. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 438...
  • Page 439 — — CHPOL CHSYNC — — CLPOL CLSYNC — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. Legend: DSM4 available on PIC16LF1777/9 only. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 439...
  • Page 440: Master Synchronous Serial Port (Mssp) Module

    Clock Select Edge SSPSSPPS Select SSPCLKPPS SSPM<3:0> T2_match Prescaler Edge 4, 16, 64 Select Baud Rate RxyPPS TRIS bit Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave mode  2015-2016 Microchip Technology Inc. DS40001819B-page 440...
  • Page 441 XMIT/RCV Bus Collision Address Match detect Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output  2015-2016 Microchip Technology Inc. DS40001819B-page 441...
  • Page 442 S, P bits Stop bit Detect (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output  2015-2016 Microchip Technology Inc. DS40001819B-page 442...
  • Page 443 The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2015-2016 Microchip Technology Inc. DS40001819B-page 443...
  • Page 444 SSPxBUF will write to both SSPxBUF and • SS must have corresponding TRIS bit set SSPSR. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.  2015-2016 Microchip Technology Inc. DS40001819B-page 444...
  • Page 445 SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x = 1010 Serial Input Buffer Serial Input Buffer (BUF) (SSPxBUF) Shift Register Shift Register (SSPSR) (SSPSR) Serial Clock Slave Select General I/O (optional) Processor 2 Processor 1  2015-2016 Microchip Technology Inc. DS40001819B-page 445...
  • Page 446 SCK pin is also the clock signal input to the peripheral. The pin selected for out- put with the RxyPPS register must also be selected as the peripheral input with the SSPCLKPPS register.  2015-2016 Microchip Technology Inc. DS40001819B-page 446...
  • Page 447 BOEN bit of the SSPxCON3 register will enable writes wake-up from Sleep. to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it.  2015-2016 Microchip Technology Inc. DS40001819B-page 447...
  • Page 448 SPI must be in Slave mode with SS pin control enabled a high level or clearing the SSPEN bit. (SSPxCON1<3:0> = 0100). FIGURE 32-7: SPI DAISY-CHAIN CONNECTION SPI Master SPI Slave General I/O SPI Slave SPI Slave  2015-2016 Microchip Technology Inc. DS40001819B-page 448...
  • Page 449 Shift register SSPSR and bit count are reset SSPxBUF to SSPSR bit 6 bit 6 bit 7 bit 0 bit 7 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF  2015-2016 Microchip Technology Inc. DS40001819B-page 449...
  • Page 450 Valid bit 6 bit 3 bit 2 bit 7 bit 5 bit 4 bit 1 bit 0 bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active  2015-2016 Microchip Technology Inc. DS40001819B-page 450...
  • Page 451 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 451...
  • Page 452  2015-2016 Microchip Technology Inc. DS40001819B-page 452...
  • Page 453 Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2015-2016 Microchip Technology Inc. DS40001819B-page 453...
  • Page 454 SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance.  2015-2016 Microchip Technology Inc. DS40001819B-page 454...
  • Page 455 FIGURE 32-12: C START AND STOP CONDITIONS Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 32-13: C RESTART CONDITION Change of Change of Data Allowed Data Allowed Restart Condition  2015-2016 Microchip Technology Inc. DS40001819B-page 455...
  • Page 456 R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.  2015-2016 Microchip Technology Inc. DS40001819B-page 456...
  • Page 457 SSPxSTAT, and the bus goes idle. Stop condition. If a Stop is sent and interrupt on Stop detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register.  2015-2016 Microchip Technology Inc. DS40001819B-page 457...
  • Page 458 FIGURE 32-14: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Bus Master sends Stop condition From Slave to Master Receiving Address Receiving Data Receiving Data ACK = 1 SSPxIF SSPxIF set on 9th Cleared by software Cleared by software falling edge of First byte...
  • Page 459 FIGURE 32-15: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Bus Master sends Stop condition Receive Address Receive Data Receive Data R/W=0 Clock is held low until CKP is set to ‘1’ SSPxIF SSPxIF set on 9th Cleared by software Cleared by software falling edge of SCL...
  • Page 460 FIGURE 32-16: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Master sends Master Releases SDA Stop condition to slave for ACK sequence Receiving Address Receiving Data Received Data ACK=1 A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SSPxIF...
  • Page 461 FIGURE 32-17: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) Master sends Stop condition Master releases R/W = 0 SDA to slave for ACK sequence Receiving Address Receive Data Receive Data A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5...
  • Page 462 SSPxIF is still set. addressed again. User software can use the BCLIF bit 15. The master sends a Restart condition or a Stop. to handle a slave bus collision. 16. The slave is no longer addressed.  2015-2016 Microchip Technology Inc. DS40001819B-page 462...
  • Page 463 FIGURE 32-18: C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Master sends Stop condition Receiving Address Automatic Transmitting Data Automatic Transmitting Data R/W = 1 A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SSPxIF Cleared by software...
  • Page 464 Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop.  2015-2016 Microchip Technology Inc. DS40001819B-page 464...
  • Page 465 FIGURE 32-19: C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) Master sends Master releases SDA Stop condition to slave for ACK sequence Receiving Address Automatic Transmitting Data Automatic Transmitting Data R/W = 1 A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SSPxIF...
  • Page 466 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission.  2015-2016 Microchip Technology Inc. DS40001819B-page 466...
  • Page 467 FIGURE 32-20: C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Master sends Stop condition Receive Data Receive Second Address Byte Receive Data Receive First Address Byte 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL is held low...
  • Page 468 FIGURE 32-21: C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) Receive First Address Byte Receive Second Address Byte Receive Data Receive Data W = 0 D6 D5 SSPxIF Set by hardware Cleared by software Cleared by software on 9th falling edge SSPxBUF can be...
  • Page 469 FIGURE 32-22: C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Master sends Master sends Stop condition Master sends Restart event not ACK Receiving Address Receiving Second Address Byte Transmitting Data Byte Receive First Address Byte ACK = 1 R/W = 0 1 1 1 1 0 A9 A8...
  • Page 470 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 – DX ‚ Master device asserts clock Master device releases clock SSPxCON1  2015-2016 Microchip Technology Inc. DS40001819B-page 470...
  • Page 471 SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt Receiving Data R/W = General Call Address SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) ’1’  2015-2016 Microchip Technology Inc. DS40001819B-page 471...
  • Page 472 Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit.  2015-2016 Microchip Technology Inc. DS40001819B-page 472...
  • Page 473 WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Because queuing of events is not allowed, Note: writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete.  2015-2016 Microchip Technology Inc. DS40001819B-page 473...
  • Page 474 Write to SEN bit occurs here At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSPxIF bit Write to SSPxBUF occurs here 2nd bit 1st bit  2015-2016 Microchip Technology Inc. DS40001819B-page 474...
  • Page 475 At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL = 1 SCL (no change) and sets SSPxIF 1st bit Write to SSPxBUF occurs here Repeated Start  2015-2016 Microchip Technology Inc. DS40001819B-page 475...
  • Page 476 (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2015-2016 Microchip Technology Inc. DS40001819B-page 476...
  • Page 477 FIGURE 32-28: C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Write SSPxCON2<0> SEN = 1 ACKSTAT in Start condition begins SSPxCON2 = 1 From slave, clear ACKSTAT bit SSPxCON2<6> SEN = 0 Transmitting Data or Second Half Transmit Address to Slave R/W = 0 of 10-bit Address ACK = 0...
  • Page 478 If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2015-2016 Microchip Technology Inc. DS40001819B-page 478...
  • Page 479 FIGURE 32-29: C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPxCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPxCON2<5>) = Write to SSPxCON2<0>(SEN = begin Start condition Set ACKEN, start Acknowledge sequence ACK from Master Master configured as a receiver SDA = ACKDT = SDA = ACKDT = by programming SSPxCON2<3>...
  • Page 480 SSPxIF bit is set 9th clock SCL brought high after T SDA asserted low before rising edge of clock to setup Stop condition Note: T = one Baud Rate Generator period.  2015-2016 Microchip Technology Inc. DS40001819B-page 480...
  • Page 481 SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master Set bus collision interrupt (BCLIF) BCLIF  2015-2016 Microchip Technology Inc. DS40001819B-page 481...
  • Page 482 SDA sampled low before Start condition. Set BCLIF. S bit and SSPxIF set because BCLIF SDA = 0, SCL = 1. SSPxIF and BCLIF are cleared by software SSPxIF SSPxIF and BCLIF are cleared by software  2015-2016 Microchip Technology Inc. DS40001819B-page 482...
  • Page 483 SCL pulled low after BRG time-out Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ BCLIF SSPxIF SDA = 0, SCL = 1, Interrupts cleared by software set SSPxIF  2015-2016 Microchip Technology Inc. DS40001819B-page 483...
  • Page 484 Cleared by software ’0’ ’0’ SSPxIF FIGURE 32-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ SSPxIF  2015-2016 Microchip Technology Inc. DS40001819B-page 484...
  • Page 485 BCLIF SDA asserted low BCLIF ’0’ ’0’ SSPxIF FIGURE 32-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) SCL goes low before SDA goes high, Assert SDA set BCLIF BCLIF ’0’ ’0’ SSPxIF  2015-2016 Microchip Technology Inc. DS40001819B-page 485...
  • Page 486 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C mode. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 486...
  • Page 487 4 MHz 100 kHz 4 MHz 1 MHz 100 kHz Refer to the I/O port electrical specifications in Table 36-10 Figure 32-7 to ensure the system is Note: designed to support I/O requirements.  2015-2016 Microchip Technology Inc. DS40001819B-page 487...
  • Page 488 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty  2015-2016 Microchip Technology Inc. DS40001819B-page 488...
  • Page 489 When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. SSP1ADD values of 0, 1 or 2 are not supported for I C mode. SSP1ADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2015-2016 Microchip Technology Inc. DS40001819B-page 489...
  • Page 490 For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I C module is not in the Idle mode, this bit may not be Note 1: set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).  2015-2016 Microchip Technology Inc. DS40001819B-page 490...
  • Page 491 This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2015-2016 Microchip Technology Inc. DS40001819B-page 491...
  • Page 492 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2015-2016 Microchip Technology Inc. DS40001819B-page 492...
  • Page 493: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (Eusart)

    SPxBRGH SPxBRGL BRGH X 1 1 0 BRG16 X 1 0 1 RxyPPS SYNC Note 1: In Synchronous mode the DT output and RX input PPS CSRC selections should enable the same pin.  2015-2016 Microchip Technology Inc. DS40001819B-page 493...
  • Page 494 Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.  2015-2016 Microchip Technology Inc. DS40001819B-page 494...
  • Page 495 If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. The TXIF Transmitter Interrupt flag is set Note: when the TXEN enable bit is set.  2015-2016 Microchip Technology Inc. DS40001819B-page 495...
  • Page 496 (Shift Clock) TX/CK Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag)  2015-2016 Microchip Technology Inc. DS40001819B-page 496...
  • Page 497 EUSART Transmit Data Register 495* TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 497...
  • Page 498 • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2015-2016 Microchip Technology Inc. DS40001819B-page 498...
  • Page 499 Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG.  2015-2016 Microchip Technology Inc. DS40001819B-page 499...
  • Page 500 OERR bit CREN This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word, Note: causing the OERR (overrun) bit to be set.  2015-2016 Microchip Technology Inc. DS40001819B-page 500...
  • Page 501 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 501...
  • Page 502 Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 33.4.1 Detect”). There may not be fine enough “Auto-Baud resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2015-2016 Microchip Technology Inc. DS40001819B-page 502...
  • Page 503 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 503...
  • Page 504 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2015-2016 Microchip Technology Inc. DS40001819B-page 504...
  • Page 505 Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2015-2016 Microchip Technology Inc. DS40001819B-page 505...
  • Page 506 To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock.  2015-2016 Microchip Technology Inc. DS40001819B-page 506...
  • Page 507 SP1BRG<7:0> SP1BRGH SP1BRG<15:8> TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 507...
  • Page 508 10417 0.00 10378 -0.37 10473 0.53 19.2k 19.23k 0.16 19.23k 0.16 19.20k 0.00 19.20k 0.00 57.6k 57.14k -0.79 56.82k -1.36 57.60k 0.00 57.60k 0.00 115.2k 117.64k 2.12 113.64k -1.36 115.2k 0.00 115.2k 0.00  2015-2016 Microchip Technology Inc. DS40001819B-page 508...
  • Page 509 19.2k 19.23k 0.16 19.23k 0.16 19.20k 0.00 — — — 57.6k 55556 -3.55 — — — 57.60k 0.00 — — — 115.2k — — — — — — 115.2k 0.00 — — —  2015-2016 Microchip Technology Inc. DS40001819B-page 509...
  • Page 510 10473 0.53 10417 0.00 19.2k 19.23k 0.16 19.23k 0.16 19.20k 0.00 19.23k 0.16 57.6k 57.14k -0.79 58.82k 2.12 57.60k 0.00 — — — 115.2k 117.6k 2.12 111.1k -3.55 115.2k 0.00 — — —  2015-2016 Microchip Technology Inc. DS40001819B-page 510...
  • Page 511 0 BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCxREG SPxBRGL SPxBRGH The ABD sequence requires the EUSART module to be configured in Asynchronous mode. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 511...
  • Page 512 RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2015-2016 Microchip Technology Inc. DS40001819B-page 512...
  • Page 513 If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is Note 1: still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.  2015-2016 Microchip Technology Inc. DS40001819B-page 513...
  • Page 514 TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2015-2016 Microchip Technology Inc. DS40001819B-page 514...
  • Page 515 Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.  2015-2016 Microchip Technology Inc. DS40001819B-page 515...
  • Page 516 Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. Note: FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXxREG reg TXIF bit TRMT bit TXEN bit  2015-2016 Microchip Technology Inc. DS40001819B-page 516...
  • Page 517 EUSART Transmit Data Register 495* TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 517...
  • Page 518 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART.  2015-2016 Microchip Technology Inc. DS40001819B-page 518...
  • Page 519 TRISC3 TRISC2 TRISC1 TRISC0 TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 519...
  • Page 520 If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.  2015-2016 Microchip Technology Inc. DS40001819B-page 520...
  • Page 521 EUSART Transmit Data Register 495* TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 521...
  • Page 522 TRISC3 TRISC2 TRISC1 TRISC0 TX1STA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. Legend: Page provides register information.  2015-2016 Microchip Technology Inc. DS40001819B-page 522...
  • Page 523 Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2015-2016 Microchip Technology Inc. DS40001819B-page 523...
  • Page 524: In-Circuit Serial Programming™ (Icsp™)

    If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See for more Section 6.5 “MCLR” information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 524...
  • Page 525 The 6-pin header (0.100" spacing) accepts 0.025" square pins. FIGURE 34-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Device to be Signals Programmed MCLR/V Data ICSPDAT Clock ICSPCLK To Normal Connections Isolation devices (as required).  2015-2016 Microchip Technology Inc. DS40001819B-page 525...
  • Page 526: Instruction Set Summary

    All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 35-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description Program Counter Time-Out bit Carry bit Digit Carry bit Zero bit Power-Down bit  2015-2016 Microchip Technology Inc. DS40001819B-page 526...
  • Page 527 FSR Offset instructions OPCODE k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only OPCODE  2015-2016 Microchip Technology Inc. DS40001819B-page 527...
  • Page 528 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second Note 1: cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2015-2016 Microchip Technology Inc. DS40001819B-page 528...
  • Page 529 If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions.  2015-2016 Microchip Technology Inc. DS40001819B-page 529...
  • Page 530 Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2015-2016 Microchip Technology Inc. DS40001819B-page 530...
  • Page 531 Bit Set f Syntax: [ label ] BSF 0  f  127 Operands: 0  b  7 1  (f<b>) Operation: Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.  2015-2016 Microchip Technology Inc. DS40001819B-page 531...
  • Page 532 ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None 00h  (W) Operation: 1  Z Status Affected: Description: W register is cleared. Zero bit (Z) is set.  2015-2016 Microchip Technology Inc. DS40001819B-page 532...
  • Page 533 ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’.  2015-2016 Microchip Technology Inc. DS40001819B-page 533...
  • Page 534 A ‘0’ is shifted into the MSb. If ‘d’ is ‘ 0 ’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f  2015-2016 Microchip Technology Inc. DS40001819B-page 534...
  • Page 535 Move literal to BSR Syntax: [ label ] MOVLB k 0  k  31 Operands: k  BSR Operation: Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR).  2015-2016 Microchip Technology Inc. DS40001819B-page 535...
  • Page 536 Status Affected: None wrap-around. Description: This instruction provides a way to execute a hardware Reset by The increment/decrement operation on software. FSRn WILL NOT affect any Status bits.  2015-2016 Microchip Technology Inc. DS40001819B-page 536...
  • Page 537 1110 0110 RETLW k1 ;Begin table RETLW k2 ; After Instruction • REG1 1110 0110 • 1100 1100 • RETLW kn ; End of table Before Instruction 0x07 After Instruction value of k8  2015-2016 Microchip Technology Inc. DS40001819B-page 537...
  • Page 538 Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2015-2016 Microchip Technology Inc. DS40001819B-page 538...
  • Page 539 W register. If ‘d’ register. is ‘1’, the result is stored back in When ‘f’ = 5, TRISA is loaded. register ‘f’. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded.  2015-2016 Microchip Technology Inc. DS40001819B-page 539...
  • Page 540: Electrical Specifications

    This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2015-2016 Microchip Technology Inc. DS40001819B-page 540...
  • Page 541 (Fosc 16 MHz)......................+2.5V DDMIN ............................ +5.5V DDMAX — Operating Ambient Temperature Range Industrial Temperature ............................-40°C ............................ +85°C Extended Temperature ............................-40°C ..........................+125°C See Parameter D001, DS Characteristics: Supply Voltage. Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 541...
  • Page 542 VOLTAGE FREQUENCY GRAPH, -40°C +125°C, PIC16LF1777/8/9 ONLY Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 36-7 for each Oscillator mode’s supported frequencies.  2015-2016 Microchip Technology Inc. DS40001819B-page 542...
  • Page 543 This is the limit to which V can be lowered in Sleep mode without losing RAM data. Note Figure 36-3: POR and POR Rearm with Slow Rising V Industrial temperature range only.  2015-2016 Microchip Technology Inc. DS40001819B-page 543...
  • Page 544 POR AND POR REARM WITH SLOW RISING V PORR NPOR POR REARM VLOW When NPOR is low, the device is held in Reset. Note 1: 1  s typical. VLOW 2.7  s typical.  2015-2016 Microchip Technology Inc. DS40001819B-page 544...
  • Page 545 The current through the resistor can be in k  extended by the formula I (mA) with R FVR and BOR are disabled. 8 MHz crystal/oscillator with 4x PLL enabled.  2015-2016 Microchip Technology Inc. DS40001819B-page 545...
  • Page 546 The current through the resistor can be in k  extended by the formula I (mA) with R FVR and BOR are disabled. 8 MHz crystal/oscillator with 4x PLL enabled.  2015-2016 Microchip Technology Inc. DS40001819B-page 546...
  • Page 547 The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V ADC clock source is FRC.  2015-2016 Microchip Technology Inc. DS40001819B-page 547...
  • Page 548 The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V ADC clock source is FRC.  2015-2016 Microchip Technology Inc. DS40001819B-page 548...
  • Page 549 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 549...
  • Page 550 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2015-2016 Microchip Technology Inc. DS40001819B-page 550...
  • Page 551 The MPLAB ICD 2 does not support variable V output. Circuitry to limit the ICD 2 V voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2.  2015-2016 Microchip Technology Inc. DS40001819B-page 551...
  • Page 552 Derated Power — = PD JA (2) Note 1: I is current to run the chip alone without driving any load on the output pins. 2: T = Ambient Temperature, T = Junction Temperature  2015-2016 Microchip Technology Inc. DS40001819B-page 552...
  • Page 553 T0CKI I/O PORT T1CKI MCLR Uppercase letters and their meanings: Fall Period High Rise Invalid (High-impedance) Valid High-impedance FIGURE 36-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Legend: CL=50 pF for all pins  2015-2016 Microchip Technology Inc. DS40001819B-page 553...
  • Page 554 All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2015-2016 Microchip Technology Inc. DS40001819B-page 554...
  • Page 555 3: See Figure 37-58: LFINTOSC Frequency, PIC16LF1777/8/9 Only., and Figure 37-59: LFINTOSC Frequency, PIC16F1777/8/9 Only.. FIGURE 36-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V AND TEMPERATURE ± 5% ± 3% ± 2% ± 5%  2015-2016 Microchip Technology Inc. DS40001819B-page 555...
  • Page 556 -0.25% — +0.25% These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2016 Microchip Technology Inc. DS40001819B-page 556...
  • Page 557 These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25  C unless otherwise stated. † Measurements are taken in EXTRC mode where CLKOUT output is 4 x T Note 1: Slew rate limited.  2015-2016 Microchip Technology Inc. DS40001819B-page 557...
  • Page 558 PIC16(L)F1777/8/9 FIGURE 36-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING MCLR Internal PWRT Time-out Start-up Time Internal Reset Watchdog Timer Reset I/O pins Note 1: Asserted low.  2015-2016 Microchip Technology Inc. DS40001819B-page 558...
  • Page 559 By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. Note 1: To ensure these voltage tolerances, V and V must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.  2015-2016 Microchip Technology Inc. DS40001819B-page 559...
  • Page 560 (Device in Brown-out Reset) (Device not in Brown-out Reset) Reset (due to BOR) Note 1: The delay, (T ) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE = 0). PWRT  2015-2016 Microchip Technology Inc. DS40001819B-page 560...
  • Page 561 Timers in Sync Increment mode These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2016 Microchip Technology Inc. DS40001819B-page 561...
  • Page 562 N = prescale value These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2016 Microchip Technology Inc. DS40001819B-page 562...
  • Page 563 Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 36-10 for OS17, OS18 and OS19 rise and fall times.  2015-2016 Microchip Technology Inc. DS40001819B-page 563...
  • Page 564 Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following T cycle.  2015-2016 Microchip Technology Inc. DS40001819B-page 564...
  • Page 565 Sampling Stopped AD132 Sample Note 1: If the ADC clock source is selected as FRC, a time of T is added before the ADC clock starts. This allows the SLEEP instruction to be executed.  2015-2016 Microchip Technology Inc. DS40001819B-page 565...
  • Page 566 CM06 Comparator Hysteresis CxHYS = 1 HYSTER These parameters are characterized but not tested. Response time measured with one comparator input at V /2, while the other input transitions from V Note 1:  2015-2016 Microchip Technology Inc. DS40001819B-page 566...
  • Page 567 — — CISW s Response Time Falling Edge — — s ZC05 Response Time Rising Edge — — COUT s Response Time Falling Edge — — These parameters are characterized but not tested.  2015-2016 Microchip Technology Inc. DS40001819B-page 567...
  • Page 568 (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions US125 T SYNC RCV (Master and Slave) Data-setup before CK  (DT hold time) — Data-hold after CK  (DT hold time) US126 T —  2015-2016 Microchip Technology Inc. DS40001819B-page 568...
  • Page 569 (CKP = 1 ) SP80 SP78 bit 6 - - - - - -1 SP75, SP76 MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 36-4 for load conditions.  2015-2016 Microchip Technology Inc. DS40001819B-page 569...
  • Page 570 (CKP = 1 ) SP80 bit 6 - - - - - -1 SP77 SP75, SP76 MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 36-4 for load conditions.  2015-2016 Microchip Technology Inc. DS40001819B-page 570...
  • Page 571 + 40 — — These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2016 Microchip Technology Inc. DS40001819B-page 571...
  • Page 572 These parameters are characterized but not tested. FIGURE 36-22: C BUS DATA TIMING SP100 SP102 SP103 SP101 SP90 SP106 SP107 SP92 SP91 SP110 SP109 SP109 Note: Refer to Figure 36-4 for load conditions.  2015-2016 Microchip Technology Inc. DS40001819B-page 572...
  • Page 573 SDA line T max. + T = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line is released.  2015-2016 Microchip Technology Inc. DS40001819B-page 573...
  • Page 574 PIC16(L)F1777/8/9 NOTES:  2015-2016 Microchip Technology Inc. DS40001819B-page 574...
  • Page 575: Dc And Ac Characteristics Graphs And Charts

    “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2015-2016 Microchip Technology Inc. DS40001819B-page 575...
  • Page 576 Max: 85°C + 3 4 MHz XT 4 MHz XT Typical: 25°C 1 MHz XT 1 MHz XT FIGURE 37-5: Typical, XT and EXTRC FIGURE 37-6: Maximum, XT and Oscillator, PIC16F1777/8/9 Only. EXTRC Oscillator, PIC16F1777/8/9 Only.  2015-2016 Microchip Technology Inc. DS40001819B-page 576...
  • Page 577 Fosc = 500 kHz, PIC16F1777/8/9 Only. Typical: 25°C 4 MHz Max: 85°C + 3 4 MHz 1 MHz 1 MHz FIGURE 37-11: Typical, EC Oscillator FIGURE 37-12: Maximum, EC Oscillator MP Mode, PIC16LF1777/8/9 Only. MP Mode, PIC16LF1777/8/9 Only.  Microchip Technology Inc. DS40001819B-page 577...
  • Page 578 Max: 85°C + 3 32 MHz Typical: 25°C 32 MHz 16 MHz 16 MHz 8 MHz 8 MHz FIGURE 37-17: Typical, EC Oscillator FIGURE 37-18: Maximum, EC Oscillator HP Mode, PIC16F1777/8/9 Only. HP Mode, PIC16F1777/8/9 Only.  2015-2016 Microchip Technology Inc. DS40001819B-page 578...
  • Page 579 16 MHz 16 MHz 8 MHz 8 MHz 4 MHz 4 MHz 2 MHz 2 MHz 1 MHz 1 MHz FIGURE 37-23: Typical, HFINTOSC FIGURE 37-24: Maximum, HFINTOSC Mode, PIC16LF1777/8/9 Only. Mode, PIC16LF1777/8/9 Only.  Microchip Technology Inc. DS40001819B-page 579...
  • Page 580 16 MHz Typical 8 MHz 4 MHz Typical: 25°C Max: 85°C + 3 FIGURE 37-29: Typical, HS Oscillator, FIGURE 37-30: , HS Oscillator (8 MHz + 25°C, PIC16F1777/8/9 Only. 4x PLL), PIC16LF1777/8/9 Only.  2015-2016 Microchip Technology Inc. DS40001819B-page 580...
  • Page 581 Max: 85°C + 3 Typical: 25°C Max: 85°C + 3 Typical: 25°C Max. Max. Typical Typical FIGURE 37-35: , Watchdog Timer (WDT), FIGURE 37-36: , Fixed Voltage Reference PIC16F1777/8/9 Only. (FVR), ADC, PIC16LF1777/8/9 Only.  Microchip Technology Inc. DS40001819B-page 581...
  • Page 582 Typical: 25°C Max. Max: 85°C + 3 Typical: 25°C Typical Typical FIGURE 37-41: , Brown-Out Reset FIGURE 37-42: , LP Brown-Out Reset (BOR), BORV = 1, PIC16F1777/8/9 Only. (LPBOR = 0), PIC16LF1777/8/9 Only.  2015-2016 Microchip Technology Inc. DS40001819B-page 582...
  • Page 583 Max: 85°C + 3 Max: 85°C + 3 Typical: 25°C Typical: 25°C Max. Max. Typical Typical FIGURE 37-47: , Op Amp, NP Mode FIGURE 37-48: , ADC Non-Converting, (VREFPM = 0), PIC16F1777/8/9 Only. PIC16LF1777/8/9 Only.  Microchip Technology Inc. DS40001819B-page 583...
  • Page 584 Graph represents 3 Limits Graph represents 3 Limits -40°C 125°C Typical Typical 125°C -40°C (mA) (mA) FIGURE 37-53: vs. I Over FIGURE 37-54: vs. I Over Temperature, V = 5.0V, PIC16F1777/8/9 Only. Temperature, V = 3.0V.  2015-2016 Microchip Technology Inc. DS40001819B-page 584...
  • Page 585 Typical; statistical mean @ 25°C 22,000 Min: Typical - 3 (-40°C to +125°C) Min: Typical - 3 (-40°C to +125°C) 20,000 FIGURE 37-59: LFINTOSC Frequency, FIGURE 37-60: WDT Time-Out Period, PIC16F1777/8/9 Only. PIC16F1777/8/9 Only.  Microchip Technology Inc. DS40001819B-page 585...
  • Page 586 20.0 Min. 2.65 10.0 2.60 Temperature (°C) Temperature (°C) FIGURE 37-65: Brown-Out Reset Hysteresis, FIGURE 37-66: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16F1773/6 Only. High Trip Point (BORV = 0).  2015-2016 Microchip Technology Inc. DS40001819B-page 586...
  • Page 587 1.62 Typical 1.60 Min. 1.58 Min. 1.56 1.54 Max: Typical + 3 Typical: statistical mean 1.52 Min: Typical - 3 1.50 Temperature (°C) FIGURE 37-71: PWRT Period, FIGURE 37-72: POR Release Voltage. PIC16LF1773/6 Only.  Microchip Technology Inc. DS40001819B-page 587...
  • Page 588 The FVR Stabiliztion Period applies when coming out of RESET or exiting sleep mode. -1.0 1024 (mV) Output Code FVR Stabilization Period, FIGURE 37-77: FIGURE 37-78: ADC 10-bit Mode,  PIC16LF1777/8/9 Only. Single-Ended DNL, V = 3.0V, T S, 25°C.  2015-2016 Microchip Technology Inc. DS40001819B-page 588...
  • Page 589 -1.5 -2.0 -2.0 5.0E-07 1.0E-06 2.0E-06 4.0E-06 8.0E-06 TADs FIGURE 37-83: ADC 10-bit Mode, FIGURE 37-84: ADC 10-bit Mode,  Single-Ended INL, V = 3.0V, V = 3.0V. Single-Ended DNL, V = 3.0V, T  Microchip Technology Inc. DS40001819B-page 589...
  • Page 590 Min: Typical - 3 -150 Temperature (°C) Temperature (°C) FIGURE 37-89: Temperature Indicator Slope FIGURE 37-90: Temperature Indicator Slope Normalized to 20°C, PIC16F1777/8/9 only. Normalized to 20°C, High Range, V = 3.6V, PIC16F1777/8/9 only.  2015-2016 Microchip Technology Inc. DS40001819B-page 590...
  • Page 591 Typical; statistical mean Min: Typical - 3 Temperature (°C) Offset Voltage (mV) FIGURE 37-95: Op Amp, Common Mode FIGURE 37-96: Op Amp, Offset Voltage Rejection Ratio (CMRR), V = 3.0V. Histogram, V = 3.0V, V  Microchip Technology Inc. DS40001819B-page 591...
  • Page 592 Common Mode Voltage (V) FIGURE 37-101: Op Amp, Output Drive FIGURE 37-102: Comparator Hysteresis, Strength, V = 5.0V, Temp. = 25°C, NP Mode (CxSP = 1), V = 3.0V, Typical PIC16F1777/8/9 Only. Measured Values.  2015-2016 Microchip Technology Inc. DS40001819B-page 592...
  • Page 593 Comparator Offset, FIGURE 37-108: Comparator Response Time NP Mode (CxSP = 1), V = 5.5V, Typical Over Voltage, NP Mode (CxSP = 1), Typical Measured Values from -40°C to 125°C, Measured Values. PIC16F1777/8/9 only.  Microchip Technology Inc. DS40001819B-page 593...
  • Page 594 112 128 144 160 176 192 208 224 240 Output Code Output Code FIGURE 37-113: Typical DAC INL Error, FIGURE 37-114: Typical DAC DNL Error, = 3.0V, V = External 3V. = 5.0V, V = External 5V, PIC16F1777/8/9 Only.  2015-2016 Microchip Technology Inc. DS40001819B-page 594...
  • Page 595 Temperature (°C) Temperature (°C) FIGURE 37-119: Absolute Value of DAC DNL FIGURE 37-120: Absolute Value of DAC INL Error, V = 5.0V, V , PIC16F1777/8/9 Error, V = 5.0V, V , PIC16F1777/8/9 Only. Only.  Microchip Technology Inc. DS40001819B-page 595...
  • Page 596 . 2.0V . 3.0V 0.30 Temperature (°C) Temperature (°C) FIGURE 37-125: Absolute Value of DAC DNL FIGURE 37-126: Absolute Value of DAC INL Error, V = 3.0V, V Error, V = 3.0V, V  2015-2016 Microchip Technology Inc. DS40001819B-page 596...
  • Page 597 ZCD Pin Voltage (V) FIGURE 37-131: ZCD Pin Current over ZCD FIGURE 37-132: ZCD Pin Response Time Pin Voltage, Typical Measured Values from over Current, Typical Measured Values from -40°C to 125°C. -40°C to 125°C.  Microchip Technology Inc. DS40001819B-page 597...
  • Page 598 0.01 0.05 0.00 0.00 DBR/DBF Value DBR/DBF Value FIGURE 37-135: COG Dead-Band Delay per FIGURE 37-136: COG Dead-Band Delay per Step, Typical Measured Values. Step, Zoomed to First 10 Codes, Typical Measured Values.  2015-2016 Microchip Technology Inc. DS40001819B-page 598...
  • Page 599: Development Support

    • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2015-2016 Microchip Technology Inc. DS40001819B-page 599...
  • Page 600 The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2015-2016 Microchip Technology Inc. DS40001819B-page 600...
  • Page 601 PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2015-2016 Microchip Technology Inc. DS40001819B-page 601...
  • Page 602 This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2015-2016 Microchip Technology Inc. DS40001819B-page 602...
  • Page 603: Packaging Information

    In the event the full Microchip part number cannot be marked on one line, it will Note: be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2015-2016 Microchip Technology Inc. DS40001819B-page 603...
  • Page 604 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC16F1777 XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX 1526017 YYWWNNN 40-Lead UQFN (5x5x0.5 mm) Example PIN 1 PIN 1 PIC16 F1779 1526017 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN  2015-2016 Microchip Technology Inc. DS40001819B-page 604...
  • Page 605 PIC16(L)F1777/8/9 Package Marking Information (Continued) Example 44-Lead TQFP (10x10x1 mm) 16F1779 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX 1526017 YYWWNNN  2015-2016 Microchip Technology Inc. DS40001819B-page 605...
  • Page 606  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2015-2016 Microchip Technology Inc. DS40001819B-page 606...
  • Page 607 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 607...
  • Page 608 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 608...
  • Page 609 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 609...
  • Page 610  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2015-2016 Microchip Technology Inc. DS40001819B-page 610...
  • Page 611 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 611...
  • Page 612 4x b2 0.10 C A B 4x b1 0.10 C A B 4x b2 0.10 C A B NOTE 4 0.05 BOTTOM VIEW Microchip Technology Drawing C04-0209 Rev C Sheet 1 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 612...
  • Page 613 BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 4. Outermost portions of corner structures may vary slightly. Microchip Technology Drawing C04-0209 Rev C Sheet 2 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 613...
  • Page 614 Corner Pad Width (X4) 0.90 Corner Pad Length (X4) 0.90 Distance Between Pads 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2209B  2015-2016 Microchip Technology Inc. DS40001819B-page 614...
  • Page 615  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2015-2016 Microchip Technology Inc. DS40001819B-page 615...
  • Page 616 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 616...
  • Page 617 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 617...
  • Page 618 PIC16(L)F1777/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2016 Microchip Technology Inc. DS40001819B-page 618...
  • Page 619 SEATING PLANE 0.08 C SIDE VIEW 0.10 C A B 0.10 C A B NOTE 1 44X b 0.07 C A B 0.05 BOTTOM VIEW Microchip Technology Drawing C04-103D Sheet 1 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 619...
  • Page 620 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103D Sheet 2 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 620...
  • Page 621 BSC: Basic Dimension. Theoretically exact value shown without tolerances. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-2103C  2015-2016 Microchip Technology Inc. DS40001819B-page 621...
  • Page 622 TOP VIEW 0.20 C A B SEATING PLANE 0.10 C SIDE VIEW 1 2 3 NOTE 1 44 X b 0.20 C A B BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 622...
  • Page 623 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2  2015-2016 Microchip Technology Inc. DS40001819B-page 623...
  • Page 624 Contact Pad Width (X44) 0.55 Contact Pad Length (X44) 1.50 Distance Between Pads 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B  2015-2016 Microchip Technology Inc. DS40001819B-page 624...
  • Page 625: Appendix A: Data Sheet Revision History

    31-5, 31-6, 31-7, and 32-4; Section 32.6; Tables 3, 4, 3-4, 3-6, 3-7, 3-14, 3-15, 3-18, 12-1, 12-2, 12-3, 24-4, 25-5, 27-5, 27-6, 28-1, 32-4, 36-1, 36-2, 36-7 and 36-8. Updated the Cover page. Section 20.5 rewritten. Added Characterization Data.  2015-2016 Microchip Technology Inc. DS40001819B-page 625...
  • Page 626 Microchip website www.microchip.com. Under “Support”, click “Customer Change Notification” and follow the registration instructions.  2015-2016 Microchip Technology Inc. DS40001819B-page 626...
  • Page 627 Reel option. = SSOP, 28-pin Small form-factor packaging options may be available. Please check www.microchip.com/packaging QTP, SQTP, Code or Special Requirements Pattern: small-form factor package availability, or (blank otherwise) contact your local Sales Office.  2015-2016 Microchip Technology Inc. DS40001819B-page 627...
  • Page 628 WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide Silicon Storage Technology is a registered trademark of headquarters, design and wafer fabrication facilities in Chandler and Microchip Technology Inc.

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