Microchip Technology PIC16F87XA Datasheet page 122

PIC16F87XA
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
RC7/RX/DT
bit
(pin)
Load RSR
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
RC7/RX/DT
bit
(pin)
Load RSR
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7
0Bh, 8Bh, INTCON GIE
10Bh,18Bh
0Ch PIR1 PSPIF
18h RCSTA SPEN
1Ah RCREG USART Receive Register
8Ch PIE1 PSPIE
98h TXSTA CSRC
99h SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582B-page 120
http://www.xinpian.net
bit 0 bit 1
bit 8 Stop
bit
Bit 8 = 0, Data Byte
bit 0 bit 1
bit 8 Stop
bit
Bit 8 = 1, Address Byte
Bit 6 Bit 5 Bit 4
PEIE TMR0IE INTE
(1)
ADIF RCIF TXIF
RX9 SREN CREN ADDEN
(1)
ADIE RCIE TXIE
TX9 TXEN SYNC
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Start
Stop
bit bit 0 bit 8
bit
Word 1
Bit 8 = 1, Address Byte
RCREG
Start
Stop
bit bit 0 bit 8
bit
Word 1
Bit 8 = 0, Data Byte
RCREG
Bit 3 Bit 2 Bit 1
RBIE TMR0IF INTF
SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
— BRGH TRMT
Value on
Value on:
Bit 0 all other
POR, BOR
Resets
R0IF
0000 000x 0000 000u
0000 0000 0000 0000
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
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