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PMC Read Disable
Flash Protection Range Registers (FPRR)
SPD Write Disable
ChipsetInit HECI Message
Bypass ChipsetInit Sync Reset
Table 37: Chipset Setup Menu –PCH-IO Configuration Sub-screens and Functions
Function
Second level Sub-screen / Description
PCI Express
PCI Express Clock
Configuration>
Gating>
DMI Link ASPM
Control>
PCIE Port assigned to
LAN>
Port8xh Decode>
Peer Memory Write
Enable>
Compliance Test
Mode>
PCIe-USB Glitch W/A>
PCIe Function Swap>
PCI Express Gen 3 Eq
Lanes>
PCIe Root Port #
Links to I211 Eth2
2 – Links to I211 Eth3
3
4
6 – links to I211 Eth1
7
8
9
13
14
15
16
17
21
22
23
24
Enable/disable PCI Express clock gating for each root port
Enable/disable control of active state power management of DMI link
Read only field
5
Enable/disable PCI express port 8xh decode
Enable/disable peer memory write
Enable when using compliance load board
Work around for bad USB device(s) connected behind PCIE/PEG port
Disable prevents PCIO Root port function swap.
If any function other than 0
PCIE# Cm (# = 1-20)>
PCIE# Cp (# = 1-20>)
Overrides SW EQ Settings>
PCI Express Root Port #>
Topology>
ASPM>
L1 Substates>
Gen3 Eq Phase3 Method>
UPTP>
DPTP>
ACS>
URR>
FER>
NFER>
CER>
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mITX-SKL-H – User Guide, Rev.1.1
th
is enabled, 0
th
becomes visible.
Display PCIE# Cm (# = 1-20)
Display PCIE# Cp (# = 1-20)
Enable/disable overrides SW EQ settings
Control the PCI Express root port
Identify the SATA topology if it is default or
ISATA or Flex or Direct Connect or M2
Set the ASPM level
PCI Express L1 substates settings
PCIe Gen3 equalization phase 3 method
Upstream port transmitter preset
Downstream port transmitter preset
Enable/disable access control services
Extended Capability
Enable/disable PCI Express unsupported
request reporting
Enable/disable PCI Express device fatal error
reporting
Enable/disable PCI Express device non-fatal
error reporting
Enable/disable PCI Express device non-
correctable error reporting
// 83
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