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59
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61
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63
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65
---
67
---
69
CONFIG_1
71
GND
73
GND
75
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based modules, due to the presence of the pull-up resistor on the platform).
3.3.10 M.2 Connectivity Slot: Socket 1 Key E Type 2230
M.2 Connectivity Slot - CN19
Pin
Signal
Pin
1
GND
3
USB_P4+
5
USB_P4-
7
GND
9
---
11
---
13
---
15
---
17
---
19
---
21
---
23
---
33
GND
35
PCIe3_Tx+
X86
UDOO X86 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by M.B. Copyright © 2017 SECO S.r.l.
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62
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64
---
66
---
68
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70
+3.3V_S
72
+3.3V_S
74
+3.3V_S
Signal
2
+3.3V_A
4
+3.3V_A
6
---
8
---
10
---
12
---
14
---
16
---
18
GND
20
---
22
---
32
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34
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36
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low by any module inserted in the connectivity slot, in order to ensure that the SoC makes
available the reference clock.
CONFIG_1: Configuration input signal, +3.3V_S signal with 10kΩ pull-up. This signal is
necessary to switch between the S-ATA and the PCI-e signals on the pins 41/43/47/49 of
connector CN20. When CONFIG_1 signal is high, then PCI-e x 2 interface is available on
connector CN20. When the signal is driven low, then SATA interface will be available. The
selection is automatic, since according to M.2 specifications for Socket2 SSD modules,
CONFIG_1 signal must be low for SSD based modules and high for PCI-e based modules.
The PCI-e x2 interface can be used also for different purposes other than SSD modules, but it
is important that the CONFIG_1 signal is driven properly (it can be left unconnected on PCI-e
It is possible to increase the connectivity of the UDOO x86
board by using M.2 Socket 1 Key E connectivity modules
(i.e. modules with functionalities like WiFi + Bluetooth).
The connector used for the M.2 Connectivity slot is CN19,
which is a standard 75 pin M.2 Key E connector, type
LOTES p/n APCI0076-P001A, H=4.2mm, with the pinout
shown in the table on the left.
On the UDOO x86 board there is also a Threaded Spacer which allows the placement of M.2
Socket 1 Key E connectivity modules in 2230 size.
Here following the signals related to this connectivity interface:
USB_P4+/USB_P4-: USB 2.0 Port #4 differential pair.
PCIe3_TX+/PCIe3_TX-: PCI Express lane #3, Transmitting Output Differential pair
PCIe3_RX+/PCIe3_RX-: PCI Express lane #3, Receiving Input Differential pair
PCIe3_Clock+ / PCIe3_Clock-: PCI Express Reference Clock for lane #3, Differential Pair
M.2_WAKE#: Board's Wake Input, 3.3V_A active low signal. It must be externally driven by
the Connectivity module plugged in the slot when it requires waking up the system.
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