M.2 Sata/Pci-E Slot: Socket 2 Key B Type 3042/2260 - Seco Udoo X86 User Manual

3.3.9

M.2 SATA/PCI-e Slot: Socket 2 Key B type 3042/2260

M.2 SATA/PCI-e Slot - CN20
Pin Signal Pin
1 ---
GND
3
GND
5
7 ---
9 ---
11 GND
21 ---
23 ---
25 ---
27 GND
29 PCIe1_Rx-
31 PCIe1_Rx+
33 GND
35 PCIe1_Tx-
37 PCIe1_Tx+
39 GND
41 SATA0_Rx+/PCIe0_Rx-
43 SATA0_Rx-/PCIe0_Rx+
45 GND
47 SATA0_Tx-/PCIe0_Tx-
49 SATA0_Tx+/PCIe0_Tx+
51 GND
53 PCIe0_Clock-
55 PCIe0_Clock+
57 GND
X86
UDOO X86 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by M.B. Copyright © 2017 SECO S.r.l.
Signal
2 +3.3V_S
+3.3V_S
4
---
6
8 ---
10 ---
20 ---
22 ---
24 ---
26 ---
28 ---
30 ---
32 ---
34 ---
36 ---
38 ---
40 ---
42 ---
44 ---
46 ---
48 ---
50 PLT_RST#
52 PCIE_REQ0#
54 ---
56 ---
58 ---
The mass storage capabilities of the UDOO x86 are
completed by an M.2 SSD Slot, which allow plugging M.2
Socket 2 Key B Solid State Drives with SATA interface or
PCI-e x2 interface (PCI-e x1 is also supported).
The connector used for the M.2 SATA/PCI-e slot is CN20,
which is a standard 75 pin M.2 Key B connector, type
LOTES p/n APCI0087-P001A, H=8.5mm, with the pinout
shown in the table on the left.
On the UDOO x86 board there is also a Threaded Spacer
which allows the placement of M.2 Socket 2 Key B
SATA/PCI-e modules in 2260 size.
It is possible to place also modules in 3042 size, by using a M/F Spacer which allows fixing
the M.2 module on the spacer already available on the PCB, deemed for the fixing of the M.2
connectivity slot (see next paragraph)
Here following the signals related to the SATA interface:
SATA0_Tx+/SATA0_Tx-: Serial ATA Channel #0 Transmit differential pair
SATA0_Rx+/SATA0_Rx-: Serial ATA Channel #0 Receive differential pair
10nF AC series decoupling capacitors are placed on each line of SATA differential pairs.
Here following the signals related to the PCI-e interface:
PCIe0_TX+/PCIe0_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIe0_RX+/PCIe0_RX-: PCI Express lane #0, Receiving Input Differential pair
PCIe1_TX+/PCIe1_TX-: PCI Express lane #1, Transmitting Output Differential pair
PCIe1_RX+/PCIe1_RX-: PCI Express lane #1, Receiving Input Differential pair
PCIe0_Clock+ / PCIe0_Clock-: PCI Express Reference Clock for lane #2, Differential Pair
PLT_RST#: Reset Signal that is sent from the SoC to all PCI-e devices available on the board
(i.e. the GbE controller, the PCI-e based SSD modules plugged in the CN20 slot and the
connectivity modules plugged in CN19 slot)It is a 3.3V active-low signal.
PCIe_REQ0#: PCI Express Clock Request Input, active low signal. This signal shall be driven
31