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RSio64-D
2-6. WORD CLOCK inspection
Contents: Word clock source register is cleared. (It carries
out before an inspection.)
Inside WORD CLOCK is inspected.
SLOT(MY1) WORD CLOCK is inspected.
SLOT(MY2) WORD CLOCK is inspected.
SLOT(MY3) WORD CLOCK is inspected.
SLOT(MY4) WORD CLOCK is inspected.
Exterior WORD CLOCK is inspected.
DANTE WORD CLOCK is inspected.
(Example of screen)
OUTPUT result
• Normal condition
The result is displayed in Output window as below.
* "MIN: xxxxh, MAX: xxxxh" represents a hexadecimal
counted value.
Item
Word Clock CLR
OK: FPGA WCK CLR
OK: FPGA WCK MY1
Word Clock MY1
MIN: xxxxh, MAX: xxxxh
OK: FPGA WCK MY2
Word Clock MY2
MIN: xxxxh, MAX: xxxxh
OK: FPGA WCK MY3
Word Clock MY3
MIN: xxxxh, MAX: xxxxh
OK: FPGA WCK MY4
Word Clock MY4
MIN: xxxxh, MAX: xxxxh
OK: FPGA WCK EXT
Word Clock EXT
MIN: xxxxh, MAX: xxxxh
OK: FPGA WCK DNT
Word Clock DNT
MIN: xxxxh, MAX: xxxxh
54
Character string to be displayed
• In case of failure
The result is displayed in Output window as below.
* "MIN: xxxxh, MAX: xxxxh" represents a hexadecimal
counted value.
Item
Character string to be displayed
Word Clock CLR
NG: FPGA WCK CLR
NG: FPGA WCK MY1
Word Clock MY1
MIN: xxxxh, MAX: xxxxh
NG: FPGA WCK MY2
Word Clock MY2
MIN: xxxxh, MAX: xxxxh
NG: FPGA WCK MY3
Word Clock MY3
MIN: xxxxh, MAX: xxxxh
NG: FPGA WCK MY4
Word Clock MY4
MIN: xxxxh, MAX: xxxxh
NG: FPGA WCK EXT
Word Clock EXT
MIN: xxxxh, MAX: xxxxh
NG: FPGA WCK DNT
Word Clock DNT
MIN: xxxxh, MAX: xxxxh
2-7. DM9000 Inspection
Contents: Link with DM9000 and built-in switch on Dante
board is inspected.
(Example of screen)
OUTPUT result
• Normal condition
The result is displayed in Output window as below.
* "xxx.xxx.xxx.xxx" represents an IP address.
Item
Character string to be displayed
Net State
OK: IP=xxx.xxx.xxx.xxx
• In case of failure
The result is displayed in Output window as below.
Item
Character string to be displayed
NG: Cannot get local addr
Net State
NG: Cannot convert local addr
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