Yamaha RSio64-D Service Manual page 21

PIN OUTER
NAME I/O
NO. NO.
L1 MA15 O
159
L2 MA16 O
160
L3 MA17 O
161
L4 MA18 O
162
VDD -
163 L5
VSS -
164 L9
VSS -
165 L10
VSS
166 L11 -
VSS
167 L12 -
VDD
168 L16 -
169 L17 D11 I/O
L18 D12 I/O
170
L19 D13 I/O
171
L20 D14 I/O
172
MA19 O
173 M1
MA20 O
174 M2
MA21 O
175 M3
MA22
176 M4 O
VSS
177 M5 -
VSS
178 M9 -
VSS
179 M10 -
M11 VSS -
180
M12 VSS -
181
M16 VSS -
182
D7 I/O
183 M17
D8 I/O
184 M18
D9 I/O
185 M19
D10 I/O
186 M20
187 N1 MA23/PG4 O
188 N2 MA24/PG5 O
189 N3 O
MA25/PG6
N4 O
190 MA26/PG7
N5 -
191 VCCQ
N16 -
192 VCCQ
N17 I/O
193 D3
I/O
194 N18 D4
I/O
195 N19 D5
I/O
196 N20 D6
197 P1 MCS3N/PG3 O
198 P2 MCS2N/PG2 O
199 P3 O
MCS1N/PG1
200 P4 O
MWRN/PG0
P5 -
201 VSS
P16 -
202 VSS
P17 O
203 RD/WRN
I/O
204 P18 D0
I/O
205 P19 D1
I/O
206 P20 D2
O
207 R1 MCS0N
208 R2 MRDN O
209 R3 I
BTCHG
210 R4 I/O
PA0
R5 -
211 VDD
R16 -
212 VDD
R17 O
213 WE3N/DQMUU/PH3
R18 O
214 RASLN
O
215 R19 CASLN
O
216 R20 RDN
I/O
217 T1 PA1
218 T2 PA2 I/O
219 T3 I/O
PA3
220 T4 I/O
PA4
221 T5 -
VDD
T6 -
222 VDD
T7 -
223 VSS
T8 -
224 VCCQ
-
225 T9 VSS
-
226 T10 VCCQ
-
227 T11 VCCQ
228 T12 VSS -
229 T13 VCCQ -
230 T14 -
VSS
231 T15 -
VDD
T16 -
232 VDD
T17 O
233 A0/PH4
T18 O
234 WE0N/DQMLL/PH0
O
235 T19 WE1N/DQMLU/PH1
O
236 T20 WE2N/DQMUL/PH2
I/O
237 U1 PA5
FUNCTION
Wave memory address bus 15
Wave memory address bus 16
Wave memory address bus 17
Wave memory address bus 18
Power supply +1.2 V
Ground
Power supply +1.2 V
SH2A-CPU data bus 11
SH2A-CPU data bus 12
SH2A-CPU data bus 13
SH2A-CPU data bus 14
Wave memory address bus 19
Wave memory address bus 20
Wave memory address bus 21
Wave memory address bus 22
Ground
SH2A-CPU data bus 7
SH2A-CPU data bus 8
SH2A-CPU data bus 9
SH2A-CPU data bus 10
Wave memory address bus 23
Wave memory address bus 24
Wave memory address bus 25
Wave memory address bus 26
Power supply +3.3 V
SH2A-CPU data bus 3
SH2A-CPU data bus 4
SH2A-CPU data bus 5
SH2A-CPU data bus 6
Wave memory chip select 3
Wave memory chip select 2
Wave memory chip select 1
Wave memory write enable
Ground
SH2A-CPU read/write enable
SH2A-CPU data bus 0
SH2A-CPU data bus 1
SH2A-CPU data bus 2
Wave memory chip select 0
Wave memory read enable
BOOT ROM switching control
Parallel port A0
Power supply +1.2 V
Writing byte of D31 - D24/Selecting D31 - D24 in case of SDRAM
RAS output for SDRAM
CAS output for SDRAM
SH2A-CPU read enable
Parallel port A1
Parallel port A2
Parallel port A3
Parallel port A4
Power supply +1.2 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +1.2 V
SH2A-CPU address bus 0
Writing byte of D7 - D0/Selecting D7 - D0 in case of SDRAM
Writing byte of D15 - D8/Selecting D15 - D8 in case of SDRAM
Writing byte of D23 - D16/Selecting D23 - D16 in case of SDRAM
Parallel port A5
PIN OUTER
NAME I/O
NO. NO.
238 PA6 I/O
U2
239 PA7 I/O
U3
VCCQ -
240 U4
ED1/PC1
241 U5 I/O
ED5/PC5
242 U6 I/O
ED9/PD1
243 U7 I/O
ED13/PD5
244 U8 I/O
245 U9 EA2/PK1 I
246 U10 ECSN I
247 U11 BCLK O
248 IRQ0 I
U12
249 A25 O
U13
250 A21 O
U14
A17 O
251 U15
A13
252 U16 O
VCCQ
253 U17 -
A3
254 U18 O
255 U19 A2 O
256 U20 A1 O
257 V1 PB0 I/O
258 V2 PB1 I/O
259 VCCQ -
V3
260 PB6 I/O
V4
ED2/PC2 I/O
261 V5
ED6/PC6
262 V6 I/O
263 V7 ED10/PD2 I/O
264 V8 ED14/PD6 I/O
265 V9 EA3/PK2 I
266 V10 SDI0/PK5 I
267 V11 WCLK2/SDO2 O
268 V12 I
IRQ1
269 I
V13 BW_MD0
270 O
V14 A22/PH5
O
271 V15 A18
O
272 V16 A14
273 V17 A10 O
274 V18 VCCQ -
275 V19 A5 O
276 V20 A4 O
277 W1 PB2 I/O
278 W2 VCCQ -
279 W3 I/O
PB4
280 I/O
W4 PB7
281 I/O
W5 ED3/PC3
I/O
282 W6 ED7/PC7
283 W7 ED11/PD3 I/O
284 W8 ED15/PD7 I/O
285 W9 ERDN/PK3 I
286 W10 SDI1/PK6 I
287 W11 WCLK O
288 W12 O
SYSCLK2
289 W13 I
WAITN/PK7
290 O
W14 A23/PH6
291 O
W15 A19
O
292 W16 A15
293 W17 A11 O
294 W18 A8 O
295 W19 VCCQ -
296 W20 A6 O
297 Y1 VCCQ -
298 Y2 I/O
PB3
299 Y3 I/O
PB5
300 I/O
Y4 ED0/PC0
301 I/O
Y5 ED4/PC4
302 I/O
Y6 ED8/PD0
I/O
303 Y7 ED12/PD4
304 Y8 EA1/PK0 I
305 Y9 EWRN/PK4 I
306 Y10 SDO0 O
307 Y11 SDO1 O
308 Y12 O
SYSCLK
309 Y13 I
SYI
310 Y14 O
A24/PH7
311 O
Y15 A20
312 O
Y16 A16
O
313 Y17 A12
314 Y18 A9 O
315 Y19 A7 O
316 Y20 VCCQ -
RSio64-D
FUNCTION
Parallel port A6
Parallel port A7
Power supply +3.3 V
External CPU data bus 1
External CPU data bus 5
External CPU data bus 9
External CPU data bus 13
External CPU address bus 2
External CPU chip select
Bit clock output
Interrupt input 0
SH2A-CPU address bus 25
SH2A-CPU address bus 21
SH2A-CPU address bus 17
SH2A-CPU address bus 13
Power supply +3.3 V
SH2A-CPU address bus 3
SH2A-CPU address bus 2
SH2A-CPU address bus 1
Parallel port B0
Parallel port B1
Power supply +3.3 V
Parallel port B6
External CPU data bus 2
External CPU data bus 6
External CPU data bus 10
External CPU data bus 14
External CPU address bus 3
Serial audio input 0
Word clock output 2/Serial audio output 2
Interrupt input 1
SH2A-CPU data bus width configuration
SH2A-CPU address bus 22
SH2A-CPU address bus 18
SH2A-CPU address bus 14
SH2A-CPU address bus 10
Power supply +3.3 V
SH2A-CPU address bus 5
SH2A-CPU address bus 4
Parallel port B2
Power supply +3.3 V
Parallel port B4
Parallel port B7
External CPU data bus 3
External CPU data bus 7
External CPU data bus 11
External CPU data bus 15
External CPU read enable
Serial audio input 1
Word clock output
Clock output 2
External wait input
SH2A-CPU address bus 23
SH2A-CPU address bus 19
SH2A-CPU address bus 15
SH2A-CPU address bus 11
SH2A-CPU address bus 8
Power supply +3.3 V
SH2A-CPU address bus 6
Power supply +3.3 V
Parallel port B3
Parallel port B5
External CPU data bus 0
External CPU data bus 4
External CPU data bus 8
External CPU data bus 12
External CPU address bus 1
External CPU write enable
Serial audio output 0
Serial audio output 1
Clock output
Sync. input from external device
SH2A-CPU address bus 24
SH2A-CPU address bus 20
SH2A-CPU address bus 16
SH2A-CPU address bus 12
SH2A-CPU address bus 9
SH2A-CPU address bus 7
Power supply +3.3 V
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