Yamaha RSio64-D Service Manual page 33

PIN OUTER
NAME I/O
NO. NO.
617 AD19 IO_L7N_2 I/O User I/O pin
618 AD20 IO_L3P_D0_DIN_MISO_MISO1_2 I
619 AD21 IO_L5N_2 I/O User I/O pin
620 AD22 IO_L1P_CCLK_2 I/O Configuration clock. Output in Master mode or input in Slave mode.
621 AD23 SUSPEND I
622 AD24 IO_L49P_HDC_M1DQ8_1 O
623 AD25 VCCO 1 -
624 AD26 IO_L48N_M1DQ9_1 I/O Memory controller data D[0:15] in bank 1.
625 AE1 IO_L35N_M3DQ11_3 I/O Memory controller data D[0:15] in bank 3.
626 AE2 IO_L35P_M3DQ10_3 I/O Memory controller data D[0:15] in bank 3.
627 AE3 IO_L2P_3 I/O User I/O pin
628 AE4 IO_L65P_INIT_B_2 open-
drain
629 AE5 IO_L64P_D8_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
630 AE6 GND -
631 AE7 IO_L62P_D5_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
632 AE8 VCCO 2 -
633 AE9 IO_L48P_D7_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
634 AE10 GND -
635 AE11 IO_L47P_2 I/O User I/O pin
636 AE12 VCCO 2 -
637 AE13 IO_L30P_GCLK1_D13_2 I/O • These clock pins connect to global clock buffers.
638 AE14 GND -
639 AE15 IO_L14P_D11_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
640 AE16 VCCO 2 -
641 AE17 IO_L12P_D1_MISO2_2 I
642 AE18 GND -
643 AE19 IO_L4P_2 I/O User I/O pin
644 AE20 VCCO 2 -
645 AE21 IO_L2P_CMPCLK_2 I/O Reserved for future use. Use these pins as general-purpose I/O.
646 AE22 GND -
647 AE23 IO_L74P_AWAKE_1 O
648 AE24 IO_L67P_1 I/O User I/O pin
649 AE25 IO_L52P_M1DQ14_1 I/O Memory controller data D[0:15] in bank 1.
650 AE26 IO_L52N_M1DQ15_1 I/O Memory controller data D[0:15] in bank 1.
651 AF1 GND -
652 AF2 IO_L2N_3 I/O User I/O pin
653 AF3 PROGRAM_B_2 I
654 AF4 IO_L65N_CSO_B_2 O
655 AF5 IO_L64N_D9_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
656 AF6 IO_L63N_2 I/O User I/O pin
657 AF7 IO_L62N_D6_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
658 AF8 IO_L53N_2 I/O User I/O pin
659 AF9 IO_L48N_RDWR_B_VREF_2 I
660 AF10 IO_L49N_D4_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
661 AF11 IO_L47N_2 I/O User I/O pin
662 AF12 IO_L32N_GCLK28_2 I
663 AF13 IO_L30N_GCLK0_USERCCLK_2 I
664 AF14 IO_L29N_GCLK2_2 I
665 AF15 IO_L14N_D12_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
666 AF16 IO_L13N_D10_2 I/O In SelectMAP/BPI modes, D0 through D15 are configuration data pins.
667 AF17 IO_L12N_D2_MISO3_2 I/O In Parallel modes, D1 and D2 are lower-order bits of the data bus. In SPI x4 mode, MISO2 and MISO3 are two
668 AF18 IO_L9N_2 I/O User I/O pin
669 AF19 IO_L4N_VREF_2 -
670 AF20 IO_L3N_MOSI_CSI_B_MISO0_2 I/O In SPI modes, Master Output/Slave Input (MOSI) connects from the FPGA to the SPI flash slave data input to
671 AF21 IO_L2N_CMPMOSI_2 I/O Reserved for future use. Use these pins as general-purpose I/O.
672 AF22 IO_L1N_M0_CMPMISO_2 -
673 AF23 DONE_2 I/O DONE is a bidirectional signal with an optional internal pull-up resistor.
674 AF24 IO_L74N_DOUT_BUSY_1 O
675 AF25 IO_L67N_1 I/O User I/O pin
676 AF26 GND -
In Parallel (SelectMAP and BPI) modes, D0 is the LSB of the data bus.
In Bit-serial modes, DIN is the single-data input.
In SPI mode, MISO is the Master Input/Slave Output.
In SPI x2 or x4 modes, MISO1 is the second bit of the SPI bus.
Active-High control input pin for the power-saving Suspend mode.
SUSPEND is a dedicated pin and AWAKE is a multi-function pin. Must be enabled by configuration option. When
Suspend mode is not used, connect this pin to GND.
High during configuration in BPI mode.
Power-supply pins for the output drivers (per bank).
When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of
configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has
occurred. Can be used after configuration (optional) to indicate POST_CRC status.
Ground.
Power-supply pins for the output drivers (per bank).
Ground.
Power-supply pins for the output drivers (per bank).
These pins become regular user I/Os when not needed for clocks.
• configuration data pins.
Ground.
Power-supply pins for the output drivers (per bank).
In Parallel modes, D1 and D2 are lower-order bits of the data bus. In SPI x4 mode, MISO2 and MISO3 are two
MSBs of the SPI bus.
Ground.
Power-supply pins for the output drivers (per bank).
Ground.
Status output pin for the power-saving Suspend mode. SUSPEND is a dedicated pin and AWAKE is a multi-
function pin. Unless Suspend mode is enabled in the application, AWAKE is available as user I/O.
Ground.
Active-Low asynchronous reset to configuration logic.
In Parallel modes, parallel daisy-chain chip select. In SPI mode, SPI flash chip select.
In SelectMAP mode, this is the active-low write-enable signal. After configuration and if needed, RDWR_B can
become a VREF in bank 2.
During slave SelectMAP readback, the pins become outputs when RDWR_B = 1. These pins become user I/Os
after configuration, unless the SelectMAP port is retained.
• These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks.
• These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks.
• Optional user configuration clock input in Master modes.
• These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks.
MSBs of the SPI bus.
These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.
send read commands and starting addresses. In SelectMAP mode, CSI_B is the active-low chipselect signal.
In SPI x2 or x4 modes, MISO0 is the first bit of the SPI bus.
Reserved for future use. Use these pins as general-purpose I/O.
In SelectMAP mode, BUSY indicates the device status.
In Bit-serial modes, DOUT gives configuration data to down-stream devices in a daisy chain.
Ground.
FUNCTION
RSio64-D
NAME(DM-IC301) I/O
IS96K4 I
CDI_FPGA O
C2F_A1 I
CCLK_FPGA I
SUSPEND -
NC -
VCCO -
XD[15] I/O
NC -
DEBSW[1] DG -
DEBSW[2] DG -
INIT_FPGA +3.3D -
RST_C1 O
GND -
UNLOCK1 I
VCCO -
C2F_B2 I
GND -
NC -
VCCO -
NC -
GND -
NC -
VCCO -
F2C_A0 O
GND -
RST_A1 O
VCCO -
C2F_A0 I
GND -
NC -
NC -
NC -
/CS_FPGA I
GND -
DEBSW[0] DG -
PROG_FPGA I
/CCS_FPGA I
C2F_C1 I
FS_MY1 I
ISSTOP1 I
ISSTOP3 I
NC -
OSC_B O
NC -
NC -
FS256_MY2 I
NC -
NC -
NC -
UNLOCK2 I
UNLOCK4 I
C2F_A3 I
CDO_FPGA I
OSC_A O
M0_FPGA +3.3D -
CONF_DONE O
NC -
NC -
GND -
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