Yamaha RSio64-D Service Manual page 29

PIN OUTER
NAME I/O
NO. NO.
354 P16 GND -
355 P17 IO_L56P_1 I/O User I/O pin
356 P18 IO_L56N_1 I/O User I/O pin
357 P19 GND -
358 P20 IO_L30P_A21_M1RESET_1 I/O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
359 P21 IO_L41P_GCLK9_IRDY1_M1RASN_1 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
360 P22 IO_L41N_GCLK8_M1CASN_1 O
361 P23 VCCO 1 -
362 P24 IO_L33P_A15_M1A10_1 O
363 P25 GND -
364 P26 IO_L33N_A14_M1A4_1 O
365 R1 IO_L44N_GCLK20_M3A6_3 I
366 R2 IO_L44P_GCLK21_M3A5_3 I
367 R3 IO_L46N_M3CLKN_3 O
368 R4 IO_L46P_M3CLK_3 O
369 R5 IO_L30P_3 I/O User I/O pin
370 R6 IO_L31N_VREF_3 -
371 R7 IO_L31P_3 I/O User I/O pin
372 R8 GND -
373 R9 IO_L49N_M3A2_3 O
374 R10 IO_L27P_3 I/O User I/O pin
375 R11 GND -
376 R12 VCCINT -
377 R13 GND -
378 R14 VCCINT -
379 R15 GND -
380 R16 VCCINT -
381 R17 IO_L58P_1 I/O User I/O pin
382 R18 IO_L58N_1 I/O User I/O pin
383 R19 IO_L57N_1 I/O User I/O pin
384 R20 IO_L57P_1 I/O User I/O pin
385 R21 IO_L55N_1 I/O User I/O pin
386 R22 IO_L55P_1 I/O User I/O pin
387 R23 IO_L39P_M1A3_1 O
388 R24 IO_L39N_M1ODT_1 O
389 R25 IO_L35P_A11_M1A7_1 O
390 R26 IO_L35N_A10_M1A2_1 O
391 T1 IO_L41N_GCLK26_M3DQ5_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
392 T2 VCCO 3 -
393 T3 IO_L41P_GCLK27_M3DQ4_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
394 T4 IO_L30N_3 I/O User I/O pin
395 T5 GND -
396 T6 IO_L29N_3 I/O User I/O pin
397 T7 VCCO 3 -
398 T8 IO_L29P_3 I/O User I/O pin
399 T9 IO_L27N_3 I/O User I/O pin
400 T10 IO_L25P_3 I/O User I/O pin
401 T11 VCCINT -
402 T12 GND -
403 T13 VCCINT -
404 T14 GND -
405 T15 VCCINT -
406 T16 GND -
407 T17 VCCINT -
408 T18 IO_L60P_1 I/O User I/O pin
409 T19 IO_L60N_1 I/O User I/O pin
410 T20 IO_L64P_1 I/O User I/O pin
411 T21 GND -
412 T22 IO_L59P_1 I/O User I/O pin
413 T23 IO_L53P_1 I/O User I/O pin
414 T24 IO_L46P_FCS_B_M1DQ2_1 O
415 T25 VCCO 1 -
Ground.
Ground.
• Memory controller reset in bank 4.
clocks.
• Used with LogiCORE IP for PCI designs.
• Memory controller active-Low column address strobe in bank 3.
• These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller active-Low column address strobe in bank #.
Power-supply pins for the output drivers (per bank).
• Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1.
Ground.
• Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1.
• These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
• These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
Memory controller active-Low clock in bank 3.
Memory controller clock in bank 3.
These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.
Ground.
Memory controller address A[0:14] in bank 3.
Ground.
Power-supply pins for the internal core logic.
Ground.
Power-supply pins for the internal core logic.
Ground.
Power-supply pins for the internal core logic.
Memory controller address A[0:14] in bank 1.
Memory controller on-die termination control for external memory in bank 1.
• Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1.
• Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1.
clocks.
• Memory controller data D[0:15] in bank 3.
Power-supply pins for the output drivers (per bank).
clocks.
• Memory controller data D[0:15] in bank 3.
Ground.
Power-supply pins for the output drivers (per bank).
Power-supply pins for the internal core logic.
Ground.
Power-supply pins for the internal core logic.
Ground.
Power-supply pins for the internal core logic.
Ground.
Power-supply pins for the internal core logic.
Ground.
• BPI flash chip select.
• Memory controller data D[0:15] in bank 1.
Power-supply pins for the output drivers (per bank).
FUNCTION
RSio64-D
NAME(DM-IC301) I/O
GND -
NC -
NC -
GND -
NC -
NC -
NC -
VCCO -
NC -
GND -
MD[4] I/O
SCLKFDNT I
NC -
NC -
NC -
NC -
NC -
NC -
GND -
NC -
NC -
GND -
VCCINT -
GND -
VCCINT -
GND -
VCCINT -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
MD[5] I/O
MD[6] I/O
MCLKFDNT I
VCCO -
NC -
NC -
GND -
NC -
VCCO -
NC -
NC -
NC -
VCCINT -
GND -
VCCINT -
GND -
VCCINT -
GND -
VCCINT -
NC -
NC -
NC -
GND -
NC -
NC -
NC -
VCCO -
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