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A
B
BLOCK DIAGRAM 002 (RSio64-D)
1
2
SLOT1
|
SLOT4
3
Brooklyn2
(Dante module)
CLOCK
source
4
5
6
4
28CA1-2001149439-2
C
D
FPGA (SABS)
IC301(676P)
SLOT1
SRC
TDMI
x4
SLOT4
SRC
TDMI
Dante
TDMI
SLOT1-4,Brooklyn2,WCLK IN
Clock
Generator
Brooklyn2
SLOT1–SLOT4
(Dante module)
E
Data
Data
buffer
buffer
Patch
Data
Data
buffer
buffer
(128x128)
METER
CPU I/F
CPU
F
G
SLOT1
SRC
TDMO
x4
SLOT4
SRC
TDMO
Dante
TDMO
UART
SPI
BLOCK DIAGRAM 002 (RSio64-D)
H
RSio64-D
SLOT1
|
SLOT4
Brooklyn2
(Dante module)
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