Yamaha RSio64-D Service Manual page 30

RSio64-D
PIN OUTER
NAME
NO. NO.
416 T26 IO_L46N_FOE_B_M1DQ3_1
417 U1 IO_L40N_M3DQ7_3
418 U2 IO_L40P_M3DQ6_3
419 U3 IO_L28N_3
420 U4 IO_L28P_3
421 U5 IO_L24P_3
422 U6 VCCAUX
423 U7 IO_L23N_3
424 U8 IO_L23P_3
425 U9 IO_L25N_3
426 U10 VCCINT
427 U11 GND
428 U12 IO_L50N_2
429 U13 IO_L50P_2
430 U14 VCCAUX
431 U15 IO_L42P_2
432 U16 VCCINT
433 U17 IO_L62P_1
434 U18 VCCO 1
435 U19 IO_L70P_1
436 U20 IO_L64N_1
437 U21 IO_L61P_1
438 U22 IO_L61N_1
439 U23 IO_L59N_1
440 U24 IO_L53N_VREF_1
441 U25 IO_L43P_GCLK5_M1DQ4_1
442 U26 IO_L43N_GCLK4_M1DQ5_1 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
443 V1 IO_L39N_M3LDQSN_3
444 V2 GND
445 V3 IO_L39P_M3LDQS_3
446 V4 IO_L42P_GCLK25_TRDY2_M3UDM_3
447 V5 IO_L24N_3
448 V6 IO_L17N_VREF_3
449 V7 IO_L17P_3
450 V8 IO_L19N_3
451 V9 VCCAUX
452 V10 IO_L21N_3
453 V11 IO_L52P_2
454 V12 IO_L46P_2
455 V13 IO_L44P_2
456 V14 IO_L42N_2
457 V15 IO_L18P_2
458 V16 IO_L8P_2
459 V17 IO_L62N_1
460 V18 IO_L66P_1
461 V19 IO_L66N_1
462 V20 IO_L70N_1
463 V21 VCCO 1
464 V22 IO_L71P_1
465 V23 IO_L42P_GCLK7_M1UDM_1
466 V24 IO_L45P_A1_M1LDQS_1
467 V25 GND
468 V26 IO_L45N_A0_M1LDQSN_1
469 W1 IO_L38N_M3DQ3_3
470 W2 IO_L38P_M3DQ2_3
471 W3 IO_L42N_GCLK24_M3LDM_3
472 W4 VCCO 3
473 W5 IO_L22P_3
474 W6 VCCO 3
475 W7 IO_L15N_3
476 W8 IO_L15P_3
477 W9 IO_L19P_3
478 W10 IO_L21P_3
479 W11 IO_L52N_2
480 W12 IO_L46N_2
30
I/O
O • BPI flash output enable.
• Memory controller data D[0:15] in bank 1.
I/O Memory controller data D[0:15] in bank 3.
I/O Memory controller data D[0:15] in bank 3.
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
- Power-supply pins for auxiliary circuits.
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
- Power-supply pins for the internal core logic.
- Ground.
I/O User I/O pin
I/O User I/O pin
- Power-supply pins for auxiliary circuits.
I/O User I/O pin
- Power-supply pins for the internal core logic.
I/O User I/O pin
- Power-supply pins for the output drivers (per bank).
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
- These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.
I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
clocks.
• Memory controller address A[0:14] in bank 1.
I/O Memory controller lower data strobe N in bank 3.
- Ground.
I/O Memory controller lower data strobe in bank 3.
I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Used with LogiCORE IP for PCI designs.
• Memory controller active-Low column address strobe in bank 3.
I/O User I/O pin
- These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.
I/O User I/O pin
I/O User I/O pin
- Power-supply pins for auxiliary circuits.
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
- Power-supply pins for the output drivers (per bank).
I/O User I/O pin
O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller upper data mask in bank 1.
O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller lower data strobe N in bank 1.
- Ground.
O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller lower data strobe N in bank 5.
I/O Memory controller data D[0:15] in bank 3
I/O Memory controller data D[0:15] in bank 3
I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller lower data mask in bank 3.
- Power-supply pins for the output drivers (per bank).
I/O User I/O pin
- Power-supply pins for the output drivers (per bank).
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
I/O User I/O pin
FUNCTION NAME(DM-IC301) I/O
NC -
NC -
NC -
NC -
NC -
NC -
VCCAUX -
NC -
NC -
NC -
VCCINT -
GND -
NC -
NC -
VCCAUX -
NC -
VCCINT -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
/MRD I
/WR_FPGA I
FPGA_B_TX O
VCCO -
NC -
FS256_BNC I
NC -
NC -
NC -
NC -
VCCAUX -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
NC -
VCCO -
NC -
NC -
NC -
GND -
MD[7] I/O
UART_A_RX I
UART_B_RX I
NC -
VCCO -
NC -
VCCO -
NC -
NC -
NC -
NC -
NC -
NC -