Advanced Micro Computers Am96/4016 User Manual page 63

APPENDIX A
CPU BUS BlJFFERING CHARACTERISTICS AT P2
The following output delay
and input setup times need
to be considered when inter-
facing external logic through
the P2 edge connector.
P2 Pin
BUSREQ*
VI*
NVI*
MI*
STOP*
WAIT*
NMI
NREQ*
BUSAK*
R/W*
N/S*
B/W*
AS*
OS*
STO-ST3
Delay (output)
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
Setup (input)
Ons
Ons
Ons
Ons
Ons
20ns
37ns
Valid at least 35ns before r{s-
ing edge of AS*. Addresses remain
valid at least 7Ins after rising
edge of OS*.
Output valid within 66ns after
falling edge of OS*. Input must be
valid at least 93ns before falling
edge of T3. It must remain valid
until rising edge of OS*.
______L . . . . . . .
A-1