Advanced Micro Computers Am96/4016 User Manual page 60

5-8
the count reg i ster is re-
loaded between output
pul ses, the present peri od
wi
11
not be affected, but
the subsequent peri od wi
11
reflect the new value.
The GATE input, when low,
will force the output high.
When the GATE input goes
hi gh, the counter wi
11
start from the initial
count. Thus, the GATE
input can be used to syn-
chronize the counter. When
this mode is set, the out-
put wi
11
rema in high unt i
1
after the count register is
loaded. The output then
can also be synchronized by
software.
Mode 3 Square Wave Rate Generator.
Similar to Mode 2 except
that the output will remain
high until one-half the
count has been completed
(for even numbers) and go
low for' the other hal f of
the count. If the count is
odd, the output will be
high for (N+l)/2 counts and
low for (N-l)/2 counts.
If the count register is
reloaded with a new value
during counting, this new
value will be reflected im-
mediately after the output
transition of the current
count.
Mode 4 Software-triggered strobe.
After the mode is set, the
output will be hi gh. When
the count is loaded, the
counter will begin coun-
t i ng. On termi na
1
count,
the output will go low for
one input clock peri od ,
then will go high again.
If the count register is
reloaded between output
pulses the present period
wi
11
not be affected, but
the subsequent peri od wi
11
reflect the new value. The
count will be inhibited
while the gate input is
low. Reloading the counter
register will restart coun-
ting beginning with the new
number.
Mode 5 Hardware-triggered strobe
The counter will start
count i ng after the ri sing
edge of the tri gger input
and will go low for one
clock peri od when the ter-
mi na
1
count is reached.
The counter is retrigger-
able. The output will not
go low until the full count
after the rising edge of
any trigger.
The format of the control byte is shown
in table 5-9; the various bits in the
control byte are defined by table 5-10.
Counter 0 is not initialized by the
Monitor during power-up. It is
available for use at P5 and must be
programmed, if used, in the same manner
described above. There are two inputs
(clock and gate) and one output
available. A jumper is provided on the
Evaluation Board for tieing the clock
input to the same 2MHz clock used in
channels
1
and 2.
The current counter values at each
channel can ,be read while actively
count i ng in the fo
11
owi ng manner:
first, the control byte shown in table
5-11 is written to the control register
(FE7) in order to
1
atch the current
val ue. Then the counter is read by
addressing it as shown in table 5-12.