Advanced Micro Computers Am96/4016 User Manual page 59

Mode 2 Rate Generator
indicates character sync has
been achieved and the Am9551 is
ready for data.
After initial ization, always check the
status of the TxRDY bit prior to writ-
ing data or a new command word to the
Am9551. The TxRDY bit must be true to
prevent overwriting and subsequent loss
of commands or data. The TxRDY is
inactive until initialization has been
completed.
Refer to the AMD Am8251/Am9551 Data
Sheet for more details.
5-3. COUNTER/TIMER
The Am8253 provides three counter/timer
channels using a 2MHz clock input de-
rived from the 4MHz CPU c: lock. Two of
the three counter outputs drive the
transmit and receive clock inputs of
the two Am9551 USARTs at 9600 baud;
counter 1 is attached to the USART at
P6, and counter 2 is attached to the
USART at P5. The third counter output,
together with its associated gate and
clock inputs, are available for ex-
ternal use on P5 together with the ser-
ial port.
A 16-bit binary counter in each channel
counts down at the clock input rate and
generates a signal when reaching zero.
Al ternat ively, a 4-decade BCD counter
can be used.
There are fi ve modes associ ated wi th
the manner in which signals are output:
Mode
a
I nterrupt on termi na1 count
The output \'Ii 11 be
1
nl-
tially low after the mode-
set operation. After the
count is loaded into the
se1ected count regi ster,
the output will remain low
and the counter will count.
When terminal count is
Mode 1
reached, the output will
go high and remain high
until the selected count
register is reloaded with
the mode.
Rel oadi ng a counter regi s-
ter during counting results
in the following:
(1) Load 1st byte stops
the current counting.
(2) Load 2nd byte starts
the new count.
The GATE input wi 11 enable
the count i ng when high and
inhibit counting when low.
Programmable One-Shot
The output wi 11 go low on
the count following the
rising edge of the GATE
input.
The output will go high on
the terminal count. If a
new count val ue is loaded
while the output is low it
wi 11 not affect the dura-
tion of the one shot pulse
until the succeeding trig-
ger. The current count can
be read at any time without
affecting the one-shot
pulse.
The one-shot is retri gger-
able, hence the output
will remain low for the
full count after any rising
edge of the gate input.
Divide by N counter. The
output will be low for one
peri ad of the input clock.
The peri ad from one output
pulse to the next equals
the number of input counts
in the count register. If
5-7