Table of Contents
Advertisement
These address 1i nes are gated by the
decoded status signal 1/0*, indicating
an input or output cycle (either one).
In order to be compatible! with the
peripheral chips, two control strobes,
IOR* and IOW* are generated from the
R/W* line when 1/0* is active, and they
are gated by DS* as illustrated in the
CPU
Functions
discussion
above.
Furthermore, the last eight groups are
decoded as wri te-on1
y
pOl"ts by gat i ng
..
with the IOW* strobe.
The complete list of I/O port addresses
is shown in table
4-1.
The range of
four contiguous addresses in each group
is first shown.
If the device uses the
AO or Al
lines for direct addres-
sing of channels or registers within
the circuit, these are listed below the
group range.
A15
A14
-----.~
----------------------_e_-+----
A13
--------:...
~
- - - - - - - - - - - - - - - - - - - - - - t l I - - t - t - - - - -
A12
ON-BOARD
..
- - - - - - - - - - - - - - - - - _ - - + - - + - - - 1 1 - - - -
OFF-BOARD
MREQ*
..
INH'~
..
--Q
P2
Figure
4-~t
Customizing Off-Board Memory References
4-5
Advertisement
Table of Contents
