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CHAPTER 4
PRINCIPLES OF OPERATION
4-1. POWER-UP SEQUEINCE
The Evaluation Board requires three
input voltages at the PI edge conector.
Their use is shown below:
+12V - RAM and serial I/O circuits
at P6. If consoles are attached to both
P5 and P6, without the keyboard/display
at P4, the first console to respond be-
comes the system console and gets all
output.
4-2. CPU FUNCTIONS
The
1
i st of CPU pi ns below describes
which pins are used for the internal
functions of the Evaluation Board.
All
pins, after buffering, are available
for external use at the P2 edge con-
nector.
-12V - RS232C and TTY interfaces.
-5V for RAM is cieri ved from
this voltage.
·t5V
-
TTL
The ground (GND) pins at PI, P2, P3 and
P4 are tied together \AJ'ith the Signal
Ground pins at P5 and P6.
They require
external ground at Pl.
The Chassis
ground pi ns at P5 and P6 can be
j
ump-
ered into this ground plane as shown in
fi gure 2-4.
.
When the board is powered up, an RC
network generates a reset to the CPU
and to the programmable parallel and
serial I/O devices.
The CPU's flag and
control \vord (FCW) is in'itialized, with
only the System/Normal flag set to Sys-
tem Mode.
The Monitor program then be-
gins execution.
The Monitor writes a value to the CPU's
refresh counter that causes refresh at
30-microsecond intervals.
The program
status area poi nter (i nterrupt vector
table) is also written.
Then, the Mon-
itor writes control bytes to the Am8253
counter/timer, the two Am955l serial
I/O ci rcui ts, and the Am8255A parall el
I/O circuit.
It also samples a line to
see if the optional keyboard/display
console is present at P4 (when present,
it receives all output).
The Monitor then sets the user's pro-
gram counter to 1000 hex and sends a
command prompt to ei theY' the keyboard/
display (if attached) or to the console
AS*
DS*
MREQ*
R/W*
- (output, three-state).
Us'ed in the normal way to
indicate
valid
addresses,
and
to
demultiplex
the
address/ data buses.
- (output, three-state).
Used in the normal way to
indicate valid data, and to
demultiplex the addreess/
data
buses.
Figure
4-1
shows how it is also used
with R/W* and 1/0* (a line
decoded
from
the
STO-
ST3 lines) to decode the
IOR* and IOW* 1ines which
gate the Am8255A,
Am955l
and Am8253 circuits.
- (output, three-state).
Used in the normal way to
gate memory.
- (output, three-state).
Used with DS* and
1/0*.
See fi gure 4-1. RAM R/W*,
which is forced high during
memory refresh, is deri ved
from this line.
4-1
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