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line.
The INH* line is normally an
output on P2 duri ng memory references
to the on-board memory space (0-5FFF);
this disables off-board memory, but it
can be jumpered (see figure 2-4) to be-
come an input and thereby give priority
to off-board memory.
The internal data bus services on-board
memory (16 bits) and I/O ports (lower 8
bits).
A 16-bit hardware breakpoint
register sits between the internal data
bus and the address bus.
When loaded
through the data bus with a hardware
breakpoint address (the Bx command), it
generates a non-maskab1e interrupt to
the CPU upon seeing that address on the
addr'ess bus.
4-4. MEMORY
Figure 3-1 shows the allocation of
memory space on the board.
The ROM
Monitor occupies addresses O-OFFF. The
opt
i
onal ROM Assembler occupi es 1000-
2FFF. There is an empty hole at 3000-
3FFF due to lack of space on the board
for add it i ona1 memory.
RAM occupi es
4000-5FFF, with up to hex 400 low bytes
used by working storage for the ROM
programs and CPU st ack po inter. (i. e. ,
up to hex address 4200.)
RAM memory is refreshed at 30-mi cro-
second intervals by the CPU, according
to the Monitor's initialization of the
CPU's fresh counter.
ROMs are disabled
during this refresh.
Since there is
only one row of RAM, the internal data
bus is sourced only by the RAM duri ng
refresh. Care shoul d be taken if the
INIT* input on PI is enabled by jumpers
14 and 15 (figure 2-4): this causes a
CPU reset, duri ng wh i ch memory refresh
ceases.
Each memory address conta ins an 8-bi t
byte.
For a RAM read, both high and
low bytes of the word-ori ented memory
are enabled, irrespective of whether
the operation is on a byte or a word.
In a byte. write to RAM, however, only
4-4
the high or low byte of memory is
enab1ed (i nterna1 data bus 1i nes IOl5
-108
or
1°7-1°0,
respectively).
By contrast, all ROM transfers enabl e
the entire word.
A single Wait state is inserted betwen
clock cycles T2 and T3 during on-board
memory cycl es, but it can be di sab 1ed
by a jumper (figure 2-4).
An INH* line is present at the P2 edge
connector for inhibiting either on- or
off-board memory, depending on the use
of optional
jumpers 16,
17 and 18
(figure 2-4).
The board is shipped
with no jumpering at these connections;
therefore, the INH* line is never act-
i vated.
When jumpers 16 and 17 are
connected,
INH*O
is
an
act i ve-l ow
output at P2 during memory references
to on-board memory space (0-5FFF); this
is useful in disabling off-board memory
that overlaps this space.
When jumpers
17 and 18 are connected, INH* is an
active-low input to the on-board memory
for
all
memory references;
on-board
memory is never accessed in this case.
The INH* 1i ne can be gated off-board
with the MREQ* line and selected ad-
dress
lines
to
vary this
priority
scheme within the 0-5FFF address space.
For example, figure 4-3 shows how off-
board memory can take precedence at all
addresses
except
O-OFFF,
where
the
Monitor resides.
4-5. PERIPHERAL DECODING
Only the low-order 12 address bits on
the Eval uat ion Board are decoded for
peripherals, giving a total of up to 4K
I/O ports.
Some peripheral circuits
use
An
and Al to directly address
internal channels or registers.
There-
fore,
these two
bits are
uniformly
treated as don't-care bits for devi ce
address i-ng as a resul t, each decoded
I/O port consists of a block of four
contiguous addresses.
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