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The AmZ8002 CPU is in the center of the
board.
At the upper right are the two
Am9551 USARTs for serial I/O, surround-
ing the Am8253 counter/timer circuit
which clocks them. The Am8255A parallel
I/O circuit is in the upper left, next
to six sockets for dri
VE~r
/termi nators
on the parallel port lines.
Sixteen
Am9050C dynamic RAM circuits provide
the 8 ki
1
obytes of user memory.
The
Monitor and optional Assembler programs
are contained in six Am4716 E-PROMs.
Figure 1-2 shows a block diagram of the
board.
The system buses (address, data
and control) emerge from the CPU and
service all
circuits, terminating at
the P2.
The address and data buses,
which are multiplexed in the CPU, are
separated
into
two
separate
16-bit
buses on the board.
The diagram shows
more clearly the difference between the
P5 and P6 serial I/O ports;
one has a
counter/timer channel available and the
other can be changed from RS232C to
20mA current-loop (TTY) interfacing.
Memory-expansion boards and prototyping
boards carrying any AmZ8002-compatible
circuits (such as DMAs or even multiple
CPUs) can be attached at P2. Special-
i zed circuits can al so be attached at
P3, P5 and P6.
P5 is particularly use-
ful for event-counting process control
circuits or foreign host computers.
Figure 1-3 illustrates the range of
standard
plug-in configurations
sup-
ported by the boardls Monitor program.
If attachments to the board are limited
to anyone or more of these three
choices,
application
programming and
execution can begin immediately without
having to program the I/O circuits.
When the AmSYS 8/8 is attached for up/
down loading of programs, the Develop-
ment System
IS
console can commun i cate
with the Eval uation Board to control
all functions.
The Development System contains a com-
prehensive set of hardware and software
resources to fully utilize AmZ8000 cap-
abi
1
it i es.
The system i ncl udes dua
1
diskette drives, 64K bytes of RAM, se-
rial and parallel ports, and a multi-
master bus.
Existing programming sup-
port includes a CPM-compatible oper-
ating system with linking loader, ed-
itor and debugger and a PASCAL-like
AmZ8000
macroassemb
1
er ,
8080
macro-
assembler
and
AmZ8000
translator.
High-level languages, including PASCAL,
are available.
See the AmSYS 8/8 bro-
chure for more details.
Table 1-1 gives a summary list of spec-
ifications for the Evaluation Board
1-2. THE CPU
The AmZ8002 microprocessor is a regis-
ter-oriented CPU with exceedingly well
organized minicomputer-like
architec-
ture.
Si xteen genera l-purpose regi s-
ters, each of them two-bytes (one 16-
bit word) wide, are available to the
user.
Over 100 instructions, and 400
combinations of instructions, can be
used to manipulate data between the CPU
registers, memory and I/O.
The CPU can operate in two modes--
system and normal--with separate relo-
catable stacks for each mode.
This al-
lows a di st i nct i on between pri vi
1
eged
and protected instructions, as well as
great flexibility
in
allocating the
system1s use of memory.
In either
mode, ten status conditions are con-
tinuously reported:
1. Internal operation
2. Instruction fetch, first word
3. Instruction fetch, subsequent word
4. Memory request, data
5. Memory request, stack
6. Memory refresh cycle
7. I/O cycle
8. Interrupt acknowledge, non-maskable
9. Interrupt acknowledge, non-vectored
10. Interrupt acknowledge, vectored
1-3
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